AGC circuit

Abstract

A linear automatic gain control circuit which can be entirely fabricated in an integrated circuit. A voltage divider has a fixed leg and a variable leg connected in series across a signal input. A non-inverting operational amplifier connected between the voltage divider and an output terminal. The variable leg is comprised of a MOSFET transistor having its source connected to the fixed leg. The junction of the source and the fixed leg carries a d.c. voltage applied from the input. A fixed operating voltage is applied to the drain of the transistor which is equal to the d.c. voltage. Signal peaks from the output of the operational amplifier are detected which are in the same polarity sense as the operating voltage. The signal peaks are stored in a storage means having a predetermined time constant. The stored signal peaks are applied to the gate of the transistor, whereby the transistor is enabled to conduct an input signal in the voltage divider symmetrically in both positive and negative directions. No external capacitor is required.

We claim: 
     
       1. An automatic gain control circuit comprising: a voltage divider having a fixed leg and a variable leg connected in series across a signal input, and a non-inverting operational amplifier connected between the voltage divider and an output terminal, the variable leg comprising an MOSFET transistor having its source connected to the fixed leg, the junction of the source and the fixed leg carrying a d.c. voltage applied from the input,   means for applying a fixed operating voltage to the drain of the transistor which is equal to the d.c. voltage,   means for detecting signal peaks from the output of the operational amplifier which are in the same polarity sense as the operating voltage,   means for storing the signal peaks in a storage means having a predetermined time constant, and for applying the stored signal peaks to the gate of the transistor, whereby the transistor is enabled to conduct an input signal in the voltage divider symmetrically in both positive and negative directions.   
     
     
       2. An automatic gain control circuit as defined in claim 1, in which the transistor is an N-channel MOSFET, the source and transistor substrate are connected together to the fixed leg, the operating voltage is positively poled, and in which the peak detector is adapted to detect positive polarity peaks. 
     
     
       3. An automatic gain control circuit as defined in claim 2 in which the fixed leg of the voltage divider is comprised of resistive means. 
     
     
       4. An automatic gain control circuit as defined in claim 2 in which the means for storing the signal peaks is comprised of a capacitor connected between the output of the detecting means and an operating voltage source which is double the voltage applied to the drain, with a discharge path comprised of a high resistive means connected between another pole of the voltage source and the output of the detecting means. 
     
     
       5. An automatic gain control circuit as defined in claim 2 in which the means for storing the signal peaks is comprised of a capacitor connected between the output of the detecting means and an operating voltage source which is double the voltage applied to the drain, with a discharge path comprised of a high resistive means connected between another pole of the voltage source and the output of the detecting means, and in which the fixed leg of the voltage divider is comprised of resistive means formed of doped polyisilicon. 
     
     
       6. An automatic gain control circuit as defined in claim 2 in which the means for storing the signal peaks is comprised of a capacitor connected between the output of the detecting means and an operating voltage source which is double the voltage applied to the drain, with a discharge path comprised of a high resistive means connected between another pole of the voltage source and the output of the detecting means, and in which the fixed leg of the voltage divider is comprised of resistive means, and further including an input buffer amplifier having one input connected to a voltage source equal to said d.c. voltage, and another input connected for receiving an input signal, and an output connected to the input of the voltage divider for applying said signal and said d.c. voltage thereto. 
     
     
       7. An automatic gain control circuit as defined in claim 2 in which the means for storing the signal peaks is comprised of an MOS capacitor connected between the output of the detecting means and an operating voltage source which is double the voltage applied to the drain, and a discharge path comprised of a current mirror means connected between another pole of the voltage source and the output of the detecting means. 
     
     
       8. An automatic gain control circuit as defined in claim 2 in which the means for storing the signal peaks is comprised of an MOS capacitor connected between the output of the detecting means and an operating voltage source which is double the voltage applied to the drain, and a discharge path comprised of a current mirror means connected between another pole of the voltage source and the output of the detecting means, and in which the fixed leg of the voltage divider is comprised of resistive means. 
     
     
       9. An automatic gain control circuit as defined in claim 2 in which the means for storing the signal peaks is comprised of an MOS capacitor connected between the output of the detecting means and an operating voltage source which is double the voltage applied to the drain, and a discharge path comprised of a current mirror means connected between another pole of the voltage source and the output of the detecting means, and in which the fixed leg of the voltage divider is comprised of resistive means, and further including an input buffer amplifier having an input connected for receiving an input signal, and an output connected to the input of the voltage divider for applying said signal and said d.c. voltage thereto. 
     
     
       10. An automatic gain control circuit as defined in claim 2 in which the means for storing the signal peaks is comprised of a capacitor connected between the output of the detecting means and an operating voltage source which is double the voltage applied to the drain, and a discharge path comprised of a current mirror circuit connected between another pole of the voltage source and the output of the detecting means, and in which the fixed leg of the voltage divider is comprised of resistive means, and further including an input amplifier having an input connected to a voltage source equal to said d.c. voltage, and another input connected for receiving an input signal, and an output connected to the input of the voltage divider for applying said signal and said d.c. voltage thereto. 
     
     
       11. An automatic gain control circuit as defined in claim 2 in which the means for storing the signal peaks is comprised of a capacitor connected between the output of the detecting means and an operating voltage source which is double the voltage applied to the drain, and a discharge path comprised of a current mirror circuit having an effective resistance of several gigaohms connected between another pole of the voltage source and the output of the detecting means, and in which the fixed leg of the voltage divider is comprised of resistive means, and further including an input amplifier having an input connected to a voltage source equal to said d.c. voltage, and another input connected for receiving an input signal, and an output connected to the input of the voltage divider for applying said signal and said d.c. voltage thereto. 
     
     
       12. An automatic gain control circuit as defined in claim 1 in which the fixed leg of the voltage divider is comprised of resistive means. 
     
     
       13. An automatic gain control circuit as defined in claim 1 in which the means for storing the signal peaks is comprised of a capacitor connected between the output of the detecting means and an operating voltage source which is double the voltage applied to the drain, with a discharge path comprised of a high resistive means connected between another pole of the voltage source and the output of the detecting means. 
     
     
       14. An automatic gain control circuit as defined in claim 1 in which the means for storing the signal peaks is comprised of a capacitor connected between the output of the detecting means and an operating voltage source which is double the voltage applied to the drain, with a discharge path comprised of a high resistive means connected between another pole of the voltage source and the output of the detecting means, and in which the fixed leg of the voltage divider is comprised of resistive means formed of doped polyisilicon. 
     
     
       15. An automatic gain control circuit as defined in claim 1 in which the means for storing the signal peaks is comprised of a capacitor connected between the output of the detecting means and an operating voltage source which is double the voltage applied to the drain, with a discharge path comprised of a high resistive means connected between another pole of the voltage source and the output of the detecting means, and in which the fixed leg of the voltage divider is comprised of resistive means, and further including an input buffer amplifier having one input connected to a voltage source equal to said d.c. voltage, and another input connected for receiving an input signal, and an output connected to the input of the voltage divider for applying said signal and said d.c. voltage thereto. 
     
     
       16. An automatic gain control circuit as defined in claim 1 in which the means for storing the signal peaks is comprised of an MOS capacitor connected between the output of the detecting means and an operating voltage source which is double the voltage applied to the drain, and a discharge path comprised of a current mirror means connected between another pole of the voltage source and the output of the detecting means. 
     
     
       17. An automatic gain control circuit as defined in claim 1 in which the means for storing the signal peaks is comprised of an MOS capacitor connected between the output of the detecting means and an operating voltage source which is double the voltage applied to the drain, and a discharge path comprised of a current mirror means connected between another pole of the voltage source and the output of the detecting means, and in which the fixed leg of the voltage divider is comprised of resistive means. 
     
     
       18. An automatic gain control circuit as defined in claim 1 in which the means for storing the signal peaks is comprised of an MOS capacitor connected between the output of the detecting means and an operating voltage source which is double the voltage applied to the drain, and a discharge path comprised of a current mirror means connected between another pole of the voltage source and the output of the detecting means, and in which the fixed leg of the voltage divider is comprised of resistive means, and further including an input buffer amplifier having an input connected for receiving an input signal, and an output connected to the input of the voltage divider for applying said signal and said d.c. voltage thereto. 
     
     
       19. An automatic gain control circuit as defined in claim 1 in which the means for storing the signal peaks is comprised of a capacitor connected between the output of the detecting means and an operating voltage source which is double the voltage applied to the drain, and a discharge path comprised of a current mirror circuit connected between another pole of the voltage source and the output of the detecting means, and in which the fixed leg of the voltage divider is comprised of resistive means, and further including an input amplifier having an input connected to a voltage source equal to said d.c. voltage, and another input connected for receiving an input signal, and an output connected to the input of the voltage divider for applying said signal and said d.c. voltage thereto. 
     
     
       20. An automatic gain control circuit as defined in claim 19 in which the resistive means, input amplifier, operational amplifier, means for detecting signal peaks, capacitor, and current mirror circuit are fabricated as a monolithic integrated circuit. 
     
     
       21. An automatic gain control circuit as defined in claim 1 in which the means for storing the signal peaks is comprised of a capacitor connected between the output of the detecting means and an operating voltage source which is double the voltage applied to the drain, and a discharge path comprised of a current mirror circuit having an effective resistance of several gigaohms connected between another pole of the voltage source and the output of the detecting means, and in which the fixed leg of the voltage divider is comprised of resistive means, and further including an input amplifier having an input connected to a voltage source equal to said d.c. voltage, and another input connected for receiving an input signal, and an output connected to the input of the voltage divider for applying said signal and said d.c. voltage thereto. 
     
     
       22. An automatic gain control circuit as defined in claim 21 in which the resistive means, input amplifier, operational amplifier, means for detecting signal peaks, capacitor, and current mirror circuit are fabricated as a monolithic integrated circuit. 
     
     
       23. An automatic gain control circuit comprising: (a) means for receiving an input signal,   (b) means for providing operating power supply positive voltage VDD and reduced or opposite polarity voltage VSS,   (c) a voltage divider for the input signal connected to the receiving means comprised of (i) a fixed resistive means having one terminal connected to the receiving means,   (ii) an N-channel MOSFET transistor having a source terminal and substrate connected to the other terminal of the resistance means, a drain connected to the voltage source of about one half the supply voltage (VDD/2), and a gate,     (d) means for applying one half the supply voltage (VDD/2) to the input of the voltage divider,   (e) a non-inverting operational amplifier circuit connected to the junction of the fixed resistance means and the source terminal, and having an AGC output terminal,   (f) a positive signal peak detector having its input connected to the output terminal of the operational amplifier, and its output connected to the gate,   (g) a charge storing integrated circuit capacitor connected between the gate and the positive voltage supply VDD,   (h) and a current mirror connected between the gate and the reduced or opposite supply voltage VSS,   the time constant of the capacitor and current mirror being about 50 milliseconds,   whereby an input signal carried by the voltage divider is compressed by variation in the resistance of the source-drain circuit of the MOSFET transistor upon variation in its gate-source voltage due to the difference in voltage across the capacitor and the function of the source and fixed resistive means.   
     
     
       24. An automatic gain control circuit as defined in claim 23, in which said means for receiving an input signal is comprised of a buffer amplifier connected to the power supply providing means for applying one half the operating voltage VDD to the fixed resistive means.