Secure integrated circuit chip with conductive shield

Abstract

An integrated circuit chip containing a secure area in which secure data is processed and/or stored, includes a semiconductive layer containing diffusions defining circuit element components; a first conductive layer coupled to the semiconductive layer to interconnect the components to thereby define circuit elements for distributing, storing processing and/or affecting the processing of secure data; and a second conductive layer overlying the circuit elements to thereby define a secure area in which the circuit elements are shielded from inspection, and coupled to the circuit elements for conducting to the circuit elements a predetermined signal that is essential to an intended function of the shielded circuit elements, whereby removal of the second conductive layer will prevent the predetermined essential signal from being provided to the circuit elements and thereby prevent the intended function.

We claim: 
     
       1. An integrated circuit chip containing a secure area in which secure data is processed and/or stored, comprising a semiconductive layer containing diffusions defining circuit element components;   a first conductive layer coupled to the semiconductive layer to interconnect the components to thereby define circuit elements for distributing, storing, processing and/or affecting the processing of secure data; and   a second conductive layer overlying the circuit elements to thereby define a secure area in which the circuit elements are shielded from inspection, and coupled to the circuit elements for conducting to the circuit elements a predetermined signal that is essential to an intended function of the circuit elements, whereby removal of the second conductive layer will prevent the predetermined essential signal from being provided to the circuit elements and thereby prevent the intended function.   
     
     
       2. An integrated circuit chip according to claim 1, wherein the predetermined signal is a power signal. 
     
     
       3. An integrated circuit chip according to claim 2, wherein the shielded circuit elements include a volatile memory for storing secure data, with the memory being powered by the predetermined power signal. 
     
     
       4. An integrated circuit chip according to claim 3, wherein each of a plurality of the volatile memories is separately coupled to only that portion of the second conductive layer that overlies such memory for receiving the predetermined power signal from only that overlying portion of the second conductive layer. 
     
     
       5. An integrated circuit chip according to claim 2, further containing a nonsecure area in which nonsecure data and control signals are processed and/or stored, wherein the shielded circuit elements include logic circuit elements for enabling transfer of nonsecure data and/or control signals between the secure area and the nonsecure area, with the logic circuit elements being powered by the predetermined power signal. 
     
     
       6. An integrated circuit chip according to claim 5, wherein each of a plurality of the logic circuit elements is separately coupled to only that portion of the second conductive layer that overlies such logic circuit element for receiving the predetermined power signal from only that overlying portion of the second conductive layer. 
     
     
       7. An integrated circuit chip according to claim 2, wherein each of a plurality of the shielded circuit elements is separately coupled to only that portion of the second conductive layer that overlies the shielded circuit element for receiving the predetermined power signal from only that overlying portion of the second conductive layer. 
     
     
       8. An integrated circuit chip according to claim 1, wherein the shielded circuit elements of the first conductive layer include a memory for storing secure data and a logic circuit for enabling data to be stored in the memory, and wherein the second conductive layer conducts a signal that is essential to the enabling function of the logic circuit, whereby removal of the second conductive layer prevents data from being stored in the memory. 
     
     
       9. An integrated circuit chip according to claim 1, wherein the shielded circuit elements include a memory having a plurality of memory locations, with a predetermined location being for the storage of unalterable secure data;   a memory control logic circuit coupled to the memory and an address bus for causing data to be stored in locations of the memory indicated by address signals provided on the address bus;   a fuse element having an initial state and an irreversibly altered state;   means coupled to the fuse element for irreversibly altering the state of the fuse element in response to a predetermined control signal; and   a decoder coupled to the fuse element, the memory control circuit and the address bus for monitoring the state of the fuse element and said address signals, and for preventing the memory control circuit from causing data to be stored in the predetermined memory location after the state of the fuse element has been altered irreversibly whenever the predetermined memory location is indicated by an address signal on the address bus.   
     
     
       10. An integrated circuit chip according to claim 9, wherein the second conductive layer further shields the memory, the memory control logic circuit, the decoder, and the fuse element from direct external access. 
     
     
       11. An integrated circuit chip according to claim 9, wherein the predetermined signal is a power signal, with the memory, the memory control logic circuit and the decoder being powered by the predetermined power signal. 
     
     
       12. An integrated circuit chip according to claim 9, wherein the predetermined signal is a power signal, and wherein the memory is a volatile memory, with the memory being powered by the predetermined power signal. 
     
     
       13. An integrated circuit chip according to claim 1, wherein the shielded circuit elements include a first memory having a plurality of memory locations, with a predetermined location being for the storage of unalterable secure data;   a second memory;   means for enabling a data pattern to be stored in the second memory;   a memory control logic circuit coupled to the first and second memories for causing data to be stored in the predetermined location of the first memory in response to a write signal whenever the second memory contains a predetermined data pattern;   means coupled to the second memory for enabling the contents of the second memory to be erased;   a fuse element having an initial state and an irreversibly altered state; and   means coupled to the fuse element for irreversibly altering the state of the fuse element in response to a predetermined control signal;   wherein the fuse element is coupled to the means for enabling a data pattern to be stored in the second memory so as to enable said data pattern storage only prior to the state of the fuse element being irreversibly altered.   
     
     
       14. An integrated circuit chip according to claim 13, wherein the second conductive layer further shields the memories, the memory control logic circuit, the enabling means, and the fuse element from direct external access. 
     
     
       15. An integrated circuit chip according to claim 13, wherein the predetermined signal is a power signal, with the memories, the memory control logic circuit and the enabling means being powered by the predetermined power signal. 
     
     
       16. An integrated circuit chip according to claim 13, wherein the predetermined signal is a power signal, and wherein the first memory is a volatile memory, with the first memory being powered by the predetermined power signal. 
     
     
       17. An integrated circuit chip according to claim 1, wherein the shielded circuit elements comprise means for enabling said storage of secure data;   a fuse element having an initial state and an irreversibly altered state; and   means coupled to the fuse element for irreversibly altering the state of the fuse element in response to a predetermined control signal;   wherein the fuse element is coupled to the enabling means so as to enable said secure data storage only prior to the state of the fuse element being irreversibly altered.   
     
     
       18. An integrated circuit chip according to claim 17, wherein the predetermined signal is a power signal, with the enabling means being powered by the predetermined power signal. 
     
     
       19. An integrated circuit chip according to claim 1, further comprising means for accessing said circuit elements for testing said circuit elements;   a fuse element having an initial state and an irreversibly altered state; and   means coupled to the fuse element for irreversibly altering the state of the fuse element in response to a predetermined control signal;   wherein the fuse element is coupled to the accessing means so as to enable said access for testing only prior to the state of the fuse element being irreversibly altered.   
     
     
       20. An integrated circuit chip according to claim 19, wherein the predetermined signal is a power signal, with the enabling means being shielded from external access by the second conductive layer and powered by the predetermined power signal. 
     
     
       21. An integrated circuit chip according to claim 1, wherein the shielded circuit elements include a given circuit element that stores, processes or affects the processing of secure data;   a fuse element having an initial state and an irreversibly altered state;   means coupled to the fuse element for irreversibly altering the state of the fuse element in response to a predetermined control signal; and   means coupled to the fuse element and the given circuit element for monitoring the state of the fuse element and for preventing the intended function of the given circuit element after the state of the fuse element has been altered irreversibly.   
     
     
       22. An integrated circuit chip according to claim 1, wherein the shielded circuit elements include a given circuit element that stores, processes or affects the processing of secure data;   a fuse element having an initial state and an irreversibly altered state;   means coupled to the fuse element for irreversibly altering the state of the fuse element in response to a predetermined control signal; and   wherein the fuse element is coupled to the given circuit element so as to enable the intended function of the given circuit element only prior to the state of the fuse element being irreversibly altered.   
     
     
       23. An integrated circuit chip according to claim 1, wherein the shielded circuit elements further include means for generating clock signals and distributing said clock signals to the shielded circuit elements that store and/or processes secure data.   
     
     
       24. An integrated circuit chip according to claim 1, wherein the shielded circuit elements further include means for controlling the provision of power to the shielded circuit elements that store and/or processes secure data.   
     
     
       25. An integrated circuit chip according to claim 24, wherein the shielded circuit elements further include means for generating clock signals and distributing said clock signals to the shielded circuit elements that store and/or processes secure data.