Integrated analog-to-digital converter

Abstract

A feedback coder, which employs simple CMOS push/pull amplifiers as gain elements, along with a bistable circuit, in its preferred embodiment takes the form of a second-order delta-sigma modulator. The output of the modulator is converted into pulse code modulated words by a finite impluse response filter which incorporates a partial coefficient generator utilizing simplified logic. The generator output is provided to an accumulator in which the stage operate at reduced speed. A simple multiplexer generates a serial output. The entire converter can be integrated on a semiconductor chip of relatively small area.

We claim: 
     
       1. A decimator comprising partial coefficient generator means and a data accumulator means, said generator means comprising input means adapted to receive an input signal, memory means having address means and data output means, counter means and shift register means, said input signal receiving means, the output of said counter means and the output of said shift register means being operably connected to said address means to address said memory to output data to said data output means, said data output means being operably connected to said data accumulator means. 
     
     
       2. The decimator of claim 1, wherein said memory means is a read only memory. 
     
     
       3. A decimator comprising partial coefficient generator means and a data accumulator means, said generator means comprising input means adapted to receive an input signal, memory means having address means and data output means, counter means and shift register means, said input signal receiving means, the output of said counter means and the output of said shift register means being operably connected to said address means, said data output means being operably connected to said data accumulator means, wherein said data output means generates a parallel output word and wherein said data accumulator means comprises means for delaying each bit of said parallel output word by an interval which is a function of the position of the bit in the output word. 
     
     
       4. The decimator of claim 3, wherein said data accumulator means comprises a plurality of stages and wherein each of said stages comprises adder means having first and second data inputs, a clock input, a sum output and a carry output, said first data input of each of said adder means receiving a different bit from the output of said delaying means, means for operably connecting said second data input of each adder means with said sum output thereof and means for operably connecting said clock input of said carry output of the adder means of said preceding stage. 
     
     
       5. The decimator of claim 4, wherein said means for connecting said second data input of each adder means to said sum output thereof comprises sum output delay means. 
     
     
       6. The decimator of claim 4, wherein said means for connecting said clock input of each adder means to said carry output of said adder means of said preceding stage comprises carry output delay means. 
     
     
       7. The decimator of claim 4, wherein said data accumulator means further comprises multiplex means comprising said given number of shift register stages respectively corresponding with said accumulator stages and connected in tandem, each of said shift register stages having an output, each of said outputs being operably connected to said sum output delay means of the corresponding stage. 
     
     
       8. The decimator of claim 7, wherein said multiplex means further comprises means for inverting the output of the last shift register stage. 
     
     
       9. A decimator for use with means for generating timing signals comprising partial coefficient generating means and data accumulator means, said generator means comprising means for receiving an input signal, means for delaying said input signal, and means for combining said input signal, said delayed input signal, and said timing signals to form the bits of a parallel output word, said data accumulator means comprising means for receiving the parallel output word. 
     
     
       10. The decimator of claim 9, wherein said timing signal generating means comprises means for generating a plurality of ordered timing pulse trains, each pulse train having a frequency which is a given fraction of the frequency of the prior pulse train in order and wherein said generator means comprises a plurality of stages, each stage comprising selector logic means, each of said logic means receiving said input signal, said delayed input signal and a different one of said pulse trains and generating one bit of said parallel output word. 
     
     
       11. The decimator of claim 10, wherein said logic means comprises means for forming the output of the logic means to be at the same state as the state of the received pulse train if the input signal is in a high state, to be the complement of the state of the pulse train if the delayed input signal is in a high state, to be a high state i both the input signal and the delayed input signal are in the high state andd to be a low state if both the input signal and the delayed input signal are in the low state. 
     
     
       12. The decimator of claim 9, wherein data accumulator means comprises means for delaying each bit of said parallel output word by an interval which is a function of the position of the bit in said output word. 
     
     
       13. The decimator of claim 12, wherein said data accumulator means comprises a plurality of stages and wherein each of said accumulator stages comprises adder means having first and second data inputs, a clock input, a sum output, and a carry output, said first data input of each of said adder means receiving a different bit from the output of said delaying means, means for operably connecting said second data input of each of said adder means with said sum output thereof, and means for operably connecting said clock input of each of said adder means to said carry output of the adder means of the preceding stage. 
     
     
       14. The decimator of claim 13, wherein said means for connecting said second data input of each of said adder means to said sum output thereof comprises sum output delay means. 
     
     
       15. The decimator of claim 14, wherein said means for connecting said clock input of each of said adder means to said carry output of said adder means of said preceding stage comprises carry output delay means. 
     
     
       16. The decimator of claim 15, wherein said data accumulator means further comprises multiplex means comprising said given number of shift register stages, respectively corresponding with said accumulator stages, and connected in tandem, each of said shift register stages having an output, each of said output being operably connected to said sum output delay means of the corresponding accumulator stage. 
     
     
       17. The decimator of claim 16, wherein said multiplex means comprises means for inverting the output of the last shift register stage. 
     
     
       18. A decimator comprising a partial coefficient generator and data accumulator means, said data accumulator means comprising means for delaying each bit of a parallel input word by an interval which is a function of the position of the bit in said word and a plurality of accumulator stages, ech of said stages comprising adder means having first and second data inputs, a clock input, a sum output and a carry output, said first data input of each of said adder means receiving a different bit of said word, means for operably connecting said second data input of each of said adder means with said sum output thereof, and means for operably connecting said clock input of each of said adder means to said carry output of the preceding adder means. 
     
     
       19. The decimator of claim 18, wherein said means for connecting said second data input of each of said adder means to said sum output thereof comprises sum output delay means. 
     
     
       20. The decimator of claim 19, wherein said means for connecting said clock input of each of said adder means to said carry output of the adder means of said preceding stage comprises carry output delay means. 
     
     
       21. The decimator of claim 18, comprising a multiplex means comprising said given number of shift register stages, respectively corresponding with said accumulator stages, and connected in tandem, each of said shift register stages having an output, each of said outputs being operably connected to said output delay means of the corresponding accumulator stage. 
     
     
       22. The decimator of claim 21, wherein said multiplex means comprises means for inverting the output of the last shift register stage. 
     
     
       23. A decimator comprising partial coefficient generator means and a data accumulator means, said generator means comprising input means adapted to receive an input signal, memory means having address means and data output means, counter means and shift register means, said input signal receiving means, the output of said counter means and the output of said shift register means being operably connected to said address means, said data output means being operably connected to said data accumulator means and wherein said counter means comprises a multi-bit counter. 
     
     
       24. A decimator comprising partial coefficient generator means and a data accumulator means, said generator means comprising input means adapted to receive an input signal, memory means having address means and data output means, counter means and shift register means, said input signal receiving means, the output of said counter means and the output of said shift register means being operably connected to said address means, said data output means being operably connected to said data accumulator means and wherein said shift register means comprises series connected shift registers, each having an output operably connected to said address means.