Speech analyzing and synthesizing apparatus utilizing differential value-based variable code length coding and compression of soundless portions

Abstract

A speech analyzing and synthesizing apparatus includes a sampling circuit for sampling an inputted speech signal, a speech analyzer for analyzing and coding the inputted speech signal, and a speech synthesizer for decoding the speech signal coded by said speech analyzer into a synthesized speech, whereby the average code length can be advantageously shortened to realize a low capacity memory and a well-analyzed and synthetized speech. Moreover, a speech recording apparatus is provided wherein a soundless section in the inputted speech signal is compressed by real time, and even a weak short-time portion in the sounded section of an inputted speech signal is not erroneously judged to be soundless, but is coded as a sounded portion.

What is claimed is: 
     
       1. A speech analyzing apparatus, comprising: sampling means for sampling an input speech signal;   speech analyzer means for analyzing and coding said sampled speech signal, including differential detector means for obtaining a differential value equal to the difference between two adjacent samples of said sampled speech signal,   judgment means for determining whether said differential value is within a coding range in which the latter of said two adjacent samples of said sampled speech signal can be coded with one of a predetermined number of codes,   coding means for encoding said latter sample when said differential value is within said coding range, and   marker code means for outputting a marker code representing the number of times said coding range must be multiplied to encompass said differential value when said differential value is outside said coding range and encoding said latter sample with one of said predetermined number of codes and said marker code.     
     
     
       2. An apparatus for storing coded sounded portions of an input speed signal while compressing soundless portions of said input speech signal in substantially real time, the apparatus comprising: input means for inputting said speech signal;   delay means, operatively connected to said input means, for delaying said input speech signal for a predetermined time period (τ);   sound discriminating means, operatively connected to said input means, for receiving said input speech signal simultaneously to said delay means, and for judging said input speech signal at a real-time (τ) to be in a soundless state or a sounded state;   encoder means, operatively connected to said delay means, for sequentially coding said input speech signal at a delayed time (t-τ);   first address means, operatively connected to said encoder means, for sequentially counting at t-τ to designate an address location of a speech code memory means at which said coded input speech signal is stored;   speech code memory means, operatively connected to said first address means, for sequentially storing said coded input speech signal at an address sequentially designated by said first address means;   state memory means, operatively connected to said sound discriminating means and said encoder means, for starting said encoder means to code said input speech signal, upon receiving a judgment from said sound discriminating means indicating input speech signal is in a sounded state, and store said input speech signal in a sounded stated at sequentially designated address locations of said speech code memory means, designated by said first address means, wherein said judgment occurs at time t and said encoding occurs at delayed time t-τ thereby allowing for a smooth transition in coding the beginning and ending of said sounded state of said input speech signal;   said sound discriminating means, upon judging said input speech signal to be in a soundless state, for a first predetermined period of time (ta), sending said judgment to said state memory means;   said first address means, upon receiving the judgment of a soundless state of said input speech signal from said state memory means, storing its address count as a startup count in a second address means;   said second address means, operatively connected to said state memory means and said first address means, for sequentially counting address locations starting from said startup count;   said state memory means, upon receiving a signal from said sound discriminating means, indicating a judgment that said input speech signal has remained in a soundless state for a second predetermined period (tb), stopping said encoder means and initiating a transfer of the address count in the second address means to the first address means, wherein said input speech signal in a soundless state is compressed in substantially real-time and only said input speech signal in a sounded state has thus been coded and stored in said speech code memory means.   
     
     
       3. An apparatus, as claimed in claim 2, further comprising: time counting means, operatively connected to said sound discriminating means, for initiating a time count upon receiving a judgment from said sound discriminating means indicating that said input speech signal is in a soundless state, and for being initialized upon receiving a judgment from said sound discriminating means indicating said input speech signal is in a sounded state.   
     
     
       4. An apparatus, as claimed in claim 2, further comprising: a switch, operatively connected to said state memory means and said first and second address means, for initiating a transfer of an address count from said first address means to said second address means when in a first state, and for initiating a transfer of an address count from said second address means to said first address means when in a second state.   
     
     
       5. An apparatus, as claimed in claim 4, wherein: said state memory means, upon receiving the judgment of a soundless state of said input speech signal, after a first predetermined time period (ta), from said sound discriminating means, switches said switch to said first state; and   said state memory means, upon receiving the judgment of a soundless state of said input speech signal, after a second predetermined time period (tb), from said sound discriminating means, switches said switch to said second state.   
     
     
       6. An apparatus, as claimed in claim 2, wherein: said sound discriminating means judges said input speech signal to be in a sounded state when said input speech signal is above a predetermined threshold; and   said sound discriminating means judgments said input speech signal to be in a soundless state when said input speech signal falls below a predetermined threshold.   
     
     
       7. A method of coding and storing sounded portions of an input speech signal and compressing soundless portions of an input speech signal in substantially real-time, said method comprising the steps of: (a) inputting a speech signal;   (b) delaying said input speech signal in a delay means;   (c) judging said input speech signal, by a judging means, simultaneous to said delaying of said input speech signal, to be in a sounded state when said input speech signal is above a predetermined threshold;   (d) sequentially encoding said delayed input speech signal, by an encoding means, upon acknowledgement of step (c) from said judging means;   (e) sequentially counting and designating addresses locations at which to store said sequentially encoded input speech signal, by utilizing a first address counter means;   (f) sequentially storing said encoded speech input signal at said sequentially designated address locations of a speech coded memory means;   (g) judging said input speech signal, by said judging means, to be in a soundless state when said input speech signal falls below a predetermined threshold;   (h) counting a first predetermined time period (ta), in a time counter means, upon receipt of a judgment that said input speech signal is in a soundless state;   (i) transferring the count of said first address counter means to a second address counter means upon receipt of a judgment that said input speech signal has been in a soundless state for a first predetermined time period (ta);   (j) sequentially counting a period of time in which said input speech signal is in a soundless state, in said second address counter means, utilizing said transferred count from said first address counter means as a starting address count;   (k) counting a second predetermined time period (tb), in said time counter means, indicating that said input speech signal remains in a soundless state;   (l) stopping the sequential encoding of said delay input speech signal, by said encoding means, and transferring the count of said second address counter means to said first address counter means, upon receipt of a judgment that said input speech signal remains in a soundless state for a second predetermined time period (tb), thereby providing coding and storing of said input speech signal in a sounded state and compression of said input speech signal, in substantially real time, while in a soundless state.   
     
     
       8. A method, as claimed in claim 7, further comprising the steps of: (m) inputting a second speech signal;   (n) repeating steps (b)-(l), thereby storing said encoded second input speech signal in a sounded state, starting at a position in said speech coded memory, directly following said sounded portion of said previously input signal, but at an address counter location which, if subtracted form said address location of the end of said sounded state of said previously input signal, would represent the amount of soundless state time existing between the first and second sounded states, thereby indicating the real-time compression of the soundless state of input signals.   
     
     
       9. A method, as claimed in claim 7, further comprising the steps of: (m) repeating step (c) by judging said input speech signal to be in a second sounded state, following said soundless state, when said input speech signal is again above said predetermined threshold;   (n) repeating steps (d)-(f) to thereby sequentially encode and store said input speech signal during a second sounded state, wherein said input signal in said second sounded state is stored at a position next to said input speech signal in said initial sounded state, in said coded memory means, whereby the difference in the address counter locations at the end of the initial sounded state and at the beginning of the second sounded state, represents the amount of soundless state time existing between the initial and second sounded states.   
     
     
       10. A speech analyzing and synthesizing apparatus, comprising: sampling means for sampling an input speech signal;   speech analyzer means for analyzing and coding said sampled speech signal, including differential detector means for obtaining a differential value equal to the difference between two adjacent samples of said sampled speech signal;   judgment means for determining whether said differential value is within a coding range in which the latter of said two adjacent samples of said sampled speech signal can be coded with one of a predetermined number of codes,   coding means for encoding said latter sample when said differential value is within said coding range, and   marker code means for outputting a marker code representing the number of times said coding range must be multiplied to encompass said differential value when said differential value is outside said coding range and encoding said said latter sample with one of predetermined number of codes and said marker code; and     speech synthesizer means for synthesizing a speech signal, including, decoder means, receiving said coded sampled speech signal, for decoding one of a predetermined number of codes in each previously encoded sample of said coded sampled speech signal;   judgment means, receiving said coded sampled speech signal simultaneously to said decoder means, for detecting whether a marker code is present in each of said previously encoded sample of said coded sampled speech signal and if said marker code is present, outputting a signal inhibiting an output signal from said decoder means;   said decoder means outputting each of said decoded samples of said coded sampled speech signal to a converting means if no inhibit signal was received from said judgment means and, decoding the number of times each of said encoded sampled of said coded sampled speech signal has been multiplied in response to said detected marker code if an inhibit signal was received from said judgment means, and outputting each of said decoded samples to said converting means;   said judgment means outputting a noninhibit signal upon detecting that said decoder means has decoded the number of times each of said encoded samples have been multiplied in response to said detected marker code;   said converting means converting each of said decoded samples of said sampled speech signal into an output speech signal.     
     
     
       11. An apparatus, as claimed in claim 10, wherein said converting means comprises: digital to analog converting means for converting each of said decoded samples into an output speech signal.