Circuitry for and method of controlling an instruction buffer in a data-processing system

Abstract

A method of controlling instructions in a data-processing system, wherein instructions including branching instructions pointing to an instruction address defining a branch address are loaded in sequence in response to a loading indicator that is always increased by no more than a prescribed difference in relation to an instruction address (BRA) that is constantly to be increased in accordance with one program runthrough and ahead of the instructions address, from instruction addresses in a main memory (MEM) into an instruction buffer memory (IBUF) and addressable therein by an instruction address. Instructions are supplied from the instruction buffer memory to an instruction decoder (IDEC) for exection, by comparing the branch address of a branching instruction while a program is being run with an instruction address range of instructions in the instruction buffer memory and, if the branch address is in said instruction address range, directly calling that addressed instruction out of the instruction buffer memory and, if the branch address is outside said instruction range, the branch address is accepted as a new loading indicator and the old instruction range is erased. The loading indicators (AP, FA) are supplied to the main memory (MEM) and at least selected bits of the loading indicator that are necessary for addressing the instruction buffer memory (IBUF) are supplied to an address pipeline (APL).

What is claimed is: 
     
       1. In a method of controlling instructions in a data-processing system, wherein instructions including branching instructions pointing to an instruction address defining a branch address are loaded in sequence, in response to a loading indicator that is always increased by no more than a prescribed difference in relation to an instruction address (BRA) that is constantly to be increased in accordance with one program runthrough and ahead of the instructions address, from instruction addresses in a main memory (MEM) into an instruction buffer memory (IBUF) and addressable therein by an instruction address, instructions are supplied from the instruction buffer memory to an instruction decoder (IDEC) for execution, by comparing the branch address of a branching instruction while a program is being run with an instruction address range of instructions in the instruction buffer memory and, if the branch address is in said instruction address range, directly calling that addressed instruction out of the instruction buffer memory and, if the branch address is outside said instruction range, the branch address is accepted as a new loading indicator and the old instruction range is erased, the improvement comprising supplying the loading indicators (AP, FA) to the main memory (MEM) and supplying at least selected bits of the loading indicators that are necessary for addressing the instruction buffer memory (IBUF) to an address pipeline (APL), supplying the at least selected bits to the instruction buffer memory after a delay corresponding to a time during which a memory-access executes memory-access procedures in the prescribed address sequence, in the form of a buffer-memory write address (IBA) and wherein the comparing of the branch address with the address range of the instructions loaded in the instruction buffer memory includes comparing the branch address with the instruction-word addresses (FA) stored in the address pipeline and decoding an associated instruction as soon as the corresponding instruction has been loaded into the instruction buffer memory when an address that corresponds to the branching address is in the address pipeline. 
     
     
       2. A method according to claim 1, wherein a buffer-mode marker (MODF) can be set and erased in accordance with an instruction and is erased by undelayed skipping instructions such that, when it is set, a branching address of a delayed skipping instruction that is half a word long is not accepted as a new loading indicator and the address range is not erased, whereas the branching address is loaded into an instruction counter such that accordingly addressed instruction will always be released for decoding once its availability has been established by the buffer being loaded as far as the instruction-counter state. 
     
     
       3. A method according to claim 2, wherein the instruction to set the buffer-mode marker (MODF) is always introduced, subject to the control of a compiler, where, in a program loop that is to be run several times and that is no longer than the size of the reserve buffer, instructions for skipping forward to skipping lines inside the loop are contained. 
     
     
       4. A method according to claim 2 or 3, wherein the particular state of the buffer-mode marker (MODF) is saved at the beginning of subsidiary programs and interrupt programs and is restored at their end. 
     
     
       5. A method according claim 1, wherein the various types of instructions have different lengths, ranging from one to three instruction-word components and wherein, before any instruction is executed, an operation component, which is the first and if necessary the second instruction-word component of the particular instruction, is decoded in relation to instruction length, and complete availability in the instruction buffer memory (IBUF) and if applicable in the address pipeline (APL) of whatever instruction-word components belong to the instruction is determined, and the instruction is not executed until all the instruction-word components of the particular instruction are available and have been transferred into the instruction decoder (IDEC), subsequent to which the instruction address is incremented by the length of the instruction. 
     
     
       6. A method according to claim 5, wherein, when the maximal instruction length is three half words nd the pipeline capacity is two whole words, availability is determined by, taking the instruction words in the pipeline into consideration, determining one-word availability and two-word availability and reporting complete availability when there is either at least two-word availability or when there is one-word availability and the instruction comprises less than three half words and the first half word is situated at the beginning of a whole word, which is indicated by a zero at the half-word address place, or the instruction is only half an instruction word long. 
     
     
       7. A method according to claim 5, wherein the number of half instruction words that are to be preliminarily loaded is always specified in the preliminary-loading instruction and the number of whole words loaded in accordance therewith into the instruction buffer memory (IBUF) is such that the specified half instruction words can be attained therein. 
     
     
       8. A method according to claim 5, wherein one type of instruction is a delayed relative skipping instruction, which always has an instruction downstream of it, whereby their joint instruction length is no more than three half words, and wherein complete availability for such a delayed skipping instruction is always considered to have been determined when the three half words are available, subsequent to which the subsidiary instruction always arrives for execution after the skipping instruction, even when a branching has been executed along with the skipping instruction. 
     
     
       9. A method according to claim 1, wherein the preliminary loading of the instruction buffer memory (IBUF) is controlled depending on a preliminary-loading instruction in accordance with a number (APRV3-0) of instruction words or instruction half words reported in the preliminary-loading instruction, for which purpose a specific difference (CMPAV) between the instruction address (PCV7-2) and the particular auxiliary loading-indicator address (APV) is constantly compared with the reported number (OPRV3-0) and the resulting preliminary-loading end releases an instruction in the instruction decoder (IDEC) for execution. 
     
     
       10. A method according to claim 9, wherein the preliminary-loading instruction is, subject to the control of a compiler, inserted into the program at whatever point is followed by a prescribed number of main-memory data instructions and/or by a program loop that is to be run several times, that is no longer than the size of the reserve buffer memory, and that has a loop-application point downstream of where the loop commences when the loop-application point is inside a prescribed range. 
     
     
       11. A method according to claim 1, wherein the loading indicator is compared, before it is increased, with a reserve indicator (BP) that always indicates the farthest instruction word back and, if the comparison results in a buffer-full signal (CAFULCV), increases the reserve indicator (BP) by a single 1 at a word-address bit. 
     
     
       12. A method according to claim 1, wherein the address pipeline (APL) is employed for the addresses (FA, RA) of instruction words to be obtained from the main memory (MEM) and of data words that are to be supplied to a register set (RGST), and characteristics associated with the instruction-word addresses (FA) are also entered into the address pipeline, in accordance with which the presence of instruction-word addresses (FA) in the address pipeline is taken into consideration during the comparison. 
     
     
       13. A method according to claim 1, wherein the main memory (MEM) has a page-by-page organization that generates an instruction-page error signal when one of the instruction addresses (ADB) supplied to the main memory (MEM) refers to a page that is not currently present in the main memory, upon which the corresponding instruction address simultaneously present in the address pipeline (APL) is erased and only one instruction is accordingly executed, setting an instruction-page error marker (IPF), in accordance with which any further preliminary loading is discontinued and, if a branching instruction to an instruction address that is not attainable in the instruction buffer memory (IBUF) is executed, the instruction-page marker is erased and, if the last available instruction that is to be executed is not a branching instruction and the instruction page error marker is still set, branching into an instruction-page error processing occurs. 
     
     
       14. In a data processing system including a main memory (MEM) having instruction words therein, an instruction buffer memory (IBUF) for receiving instruction words from the main memory (MEM), a loading-indicator register (AP, APV) storing a loading indicator (FA) for controlling the loading of instruction words from the main memory to the buffer memory, a loading-indicator adder (CTA) for indicating a prescribed maximal number of preliminary-loading words in advance of an instruction address and for constantly increasing the number of an instruction counter (PCU) for controlling the instruction words read from the buffer while a program runs, an instruction decoder (IDEC) for receiving the instruction words read from the buffer memory, wherein the instruction buffer memory has an instruction reserve memory wherein instructions that have already been executed or instruction words that have been constantly stored and skipped over remain, a second indicator register (BP, BPV) for storing a second indicator indicating the contents of the reserve memory, means for producing sum signals in the presence of a branching instruction from accordingly resulting skip-width signals (OPRV6-1) in summing stages (SUA, SUB, SUC, SUD) along with the loading indicator and the second indicator, a branching-control circuit (BRCALV, BRACHL) receptive of the sum signals for indicating that the branching address is in the preliminary loaded instruction buffer memory (IBUF) or in the instruction reserve memory and, if not, loading an initial value in the loading-indicator register (AP, APV), the improvement comprising an address pipeline for supplying the loading-address indicator (FA) to the instruction buffer memory (IBUF) and having a capacity that is dimensioned in accordance with the access time of the main memory (MEM) and a completeness-testing circuit (ILCL) receptive of any number (IFPV3, 2) of instruction words that are present from the pipeline for producing an output signal (ILCV) that reports the complete availability in the instruction buffer memory (BUF) of an instruction addressed by the instruction address and for triggering the instruction counter (PUC) to increment the instruction address by a particular instruction length. 
     
     
       15. Circuitry according to claim 14, further comprising means for writing two half words, addressed in the form of whole words, into the instruction buffer memory (IBUF) with the loading-indicator address and for reading out, with the instruction address, three half words. 
     
     
       16. Circuitry according to claim 15, wherein the instruction buffer memory (IBUF) is at least a component of an integrated circuit comprises cells (Zm, n) are arrayed in n lines and m columns of the length of half a word, wherein each pair of adjacent lines is connected by write-address lines (WEw) to output terminals of a write-address decoder (DW), each of which, subject to the control of a write-control signal (IBW), emits an output signal and that are connected to data lines (Dm, DmN), which are oriented column by column by way of write-AND circuits (TE1, TE2) such that they accept a binary cell state in a listable memory components (V1, V2), and to each output terminal of which three output-AND gates (TL1, TL2, TL3) are connected that are at the output end combined column by column into wired OR circuits and accordingly supplied to output terminals, and their other inputs are activated line-by-line by read-decoder output lines (RE, REn-1, REn-2) of a read decoder (DR) adjacently cyclically and displaced by one or two lines. 
     
     
       17. Circuitry according to claim 16, wherein the write-AND circuits (TE1, TE2) are MOS-FET's with their gate electrodes are connected to the write-decoder line (WEw). 
     
     
       18. Circuitry according to claim 16, wherein the bistable memory component (V1, V2) is a mutually feedbacked system of two inverters (V1, V2) with feedbacks that are weaker than the activation by the write-AND circuits (TE1, TE2). 
     
     
       19. Circuitry according to claim 16, 17, or 18, wherein a MOS-FET (TA) is controlled by the bistable memory component (V1, V2), three other MOS-FET's (TL1, TL2, and TL3) are on the one hand supplied to the output terminal of the first MOS-FET, create output-AND gates, are connected at the gate end in association with associated read-decoder output lines (REn, REn-1, REn-2), and are on the other hand connected column-by-column together and each column by column by means of a loading transistor (TH) that is controlled by a read-release signal (ER) to a voltage line (+U) and lead to the output terminals. 
     
     
       20. Circuitry according to claim 19, wherein registers or amplifiers (OR0, . . . , OR15; PR0, . . . , PR15; QR0, . . . , QR15) that terminate or amplify the output signals are positioned at the output terminals for every three half words. 
     
     
       21. Circuitry according to claim 16, wherein the instruction buffer memory (IBUF), the instruction-loading circuit (PFU) and the address pipeline (APL) are located in an integrated circuit. 
     
     
       22. Circuitry according to claim 15, wherein the instruction decoder decodes an instruction length (ILDV2,1) from the first and from the second instruction half word, and supplies the decoded instruction length to the completeness-testing circuit (ILCL) having means for evaluating same such that the completeness of an instruction is always considered as given when at least two words are available or when one word is available and the instruction is not a delayed skipping instruction and the instruction either comprises only one half word or, if it comprises two half words, the first half word is situated at the beginning of a word, and the position of the first half instruction word in relation to the whole instruction word is evaluated depending on the half-word address place (PCV1) of the instruction counter (PCU), and wherein, when there is completeness, the instruction length is supplied as an increment (ILCV) to the instruction counter. 
     
     
       23. Circuitry according to claim 22, wherein the instruction decoder decodes a delay skipping signal (DLYBRDV, DLYBR) and supplies same to the completeness-testing circuit to evaluate an instruction of three half words during completeness testing. 
     
     
       24. Circuitry according to claim 14, further comprising means for cyclically loading the instruction buffer memory comprising a third summer stage and wherein the loading-indicator register (AP, APV) is operated along with the loading-indicator adder (CTA) and the return indicator register (BP, BPV) along with a return-indicator adder (CTB) modulo to determine a maximal capacity of the instruction buffer memory (IBUF) and the loading indicator and a corrective 1 from the return indicator is always subtracted in the third summer (SUE) before the loading indicator is increased and, if its zero output signals that maximal capacity (CAFULV) has been attained, the return indicator is also increased by way of the return-indicator added (CTB). 
     
     
       25. Circuitry according to claim 14, wherein the number of preliminary-loading words is a particular number or a number (OPRV3-0) that can be prescribed by a preliminary-loading instruction criterion (OPLD) and further comprising a multiplexer (MPXC) controlled by the preliminary-loading instruction criterion (OPLD) for supplying the preliminary-loading words to the second summer (SUC) of the loading indicator, a loading-instruction transmission circuit (FENDL) for evaluating the overflow signal of the second summer stage such that the instruction buffer memory (IBUF) is loaded until said overflow signal (SUC7) occurs, upon which the next instruction designated by the instruction address is read and executed. 
     
     
       26. Circuitry according to claim 14, further comprising means for setting a buffer-mode marker (MODF, MODFV) by instructions and for erasing same by a control signal of an undelayed skipping instruction and means for supplying the state of the buffer-code marker to the branching-control circuit (BRCALV, BRCHL), which, when it is set and when the forward skips are delayed by the instruction length of half a word, always signals that the skipping target is attainable in the buffer memory. 
     
     
       27. Circuitry as in claim 14, wherein the summing stages include a first summer stage for subtracting the instruction address (PCV7-2) along with loading indicator (FA) and with the second indicator and second summing stage (SUC, SUD) for adding the results of the first summer stage along with a skipping width (OPRV6-1) of a branching instruction and with a correction 1 and a branching-control circuit (BRCALV, BRCHL) for connecting the sums such that, when the summing stages indicate an overflow (SUC7, SUD7) or the loading-indicator summing stage (SUC) indicates a zero result (SUCX), the branching address is the buffer-read address and otherwise the branching address is written into the loading-indicator register (AP, APV) and the second indicator register (BP, BPV and the instruction counter (PCU) and supplied by the loading-indicator register (AP, APV) to the main memory (MEM) and the address pipeline.