MOS transistor with improved radiation hardness

Abstract

An MOS transistor is disclosed which has a guard ring for prevention of source-to-drain conduction through the isolation oxide after exposure to ionizing radiation. In the described example of an n-channel transistor, a p+ region is formed at the edges of the source region in a self-aligned fashion relative to the gate electrode so as not to extend under the gate to contact the drain region. This p+ region forms a diode which retards source-drain conduction even if a channel is formed under the isolating field oxide where the gate electrode overlaps onto the field oxide. The structure may be silicided for improved series resistance. An example of the transistor formed in an SOI configuration is also disclosed.

We claim: 
     
       1. An insulated-gate field effect transistor at a surface of a semiconductor body, comprising: an insulating layer disposed at selected locations of said surface to define an active region of said semiconductor body;   a gate electrode disposed over a portion of said active region and extending onto said insulating layer;   a drain region of a first conductivity type disposed at said surface within said active region on a first side of said gate electrode, said drain region extending to the edge of said insulating layer at a location adjacent to said gate electrode;   a source region of said first conductivity type disposed at said surface within said active region on a second side of said gate elctrode;   a guard region of a second conductivity type disposed in said active region between said source region and said insulating layer at a location adjacent said gate electrode;   a channel region of said second conductivity type having a portion disposed under said gate electrode between said guard region and said drain region, and having a portion disposed under said gate electrode between said source region and said drain region, said channel region being less heavily doped than said guard region; and   a channel stop region of said second conductivity type formed under said insulating layer.   
     
     
       2. The transistor of claim 1, wherein said first conductivity type is n-type and said second conductivity type is p-type. 
     
     
       3. An insulated-gate field effect transistor at a surface of a semiconductor body, comprising: an insulating layer disposed at selected locations of said surface to define an active region of said semiconductor body;   a gate electrode disposed over a portion of said active region and extending onto said insulating layer;   a drain region of a first conductivity type disposed at said surface within said active region on a first side of said gate electrode, said drain region extending to the edge of said insulating layer at a location adjacent to said gate electrode;   a source region of said first conductivity type disposed at said surface within said active region on a second side of said gate electrode;   a guard region of a second conductivity type disposed in said active region between said source region and said insulating layer at a location adjacent said gate electrode; and   a channel region of said second conductivity type having a portion disposed under said gate electrode between said guard region and said drain region, had having a portion disposed under said gate electrode between said source region and said drain region, said channel region being less heavily doped than said guard region;   wherein the junction between said guard region and said source region is reverse-biased.   
     
     
       4. The transistor of claim 3, wherein said guard region is biased to the same voltage as said source region. 
     
     
       5. The transistor of claim 3, wherein said guard region is biased to a voltage below the voltage of said source region. 
     
     
       6. The transistor of claim 1, further comprising: a second insulating layer;   and wherein said semiconductor body is a layer of silicon disposed over said second insulating layer.   
     
     
       7. The transistor of claim 3, wherein said first conductivity type is n-type and said second conductivity type is p-type. 
     
     
       8. The transistor of claim 3, further comprising: a second insulating layer;   and wherein said semiconductor body is a layer of silicon disposed over said second insulating layer.   
     
     
       9. An insulated-gate field effect transistor at a surface of a semiconductor body, comprising: an insulating layer disposed at selected locations of said surface to define an active region of said semiconductor body;   a gate electrode disposed over a portion of said active region and extending onto said insulating layer;   a drain region of a first conductivity type disposed at said surface within said active region on a first side of said gate electrode, said drain region extending to the edge of said insulating layer at a location adjacent to said gate electrode;   a source region of said first conductivity type disposed at said surface within said active region on a second side of said gate electrode;   a guard region of a second conductivity type disposed in said active region between said source region and said insulating layer at a location adjacent said gate electrode;   a channel region of said second conductivity type having a portion disposed under said gate electrode between said guard region and said drain region, and having a portion disposed under said gate electrode between said source region and said drain region, said channel region being less heavily doped than said guard region, and   a silicide film disposed over said drain region, said source region, and said guard region.   
     
     
       10. The transistor of claim 9, wherein said first conductivity type is n-type and said second conductivity type is p-type. 
     
     
       11. The transistor of claim 9, further comprising: a second insulating layer;   and wherein said semiconductor body is a layer of silicon disposed over said second insulating layer.