Self-aligned interconnects for semiconductor devices

Abstract

A novel process is provided to fabricate interconnections (46c) in transistors (14) having self-aligned, planarized contacts (46s, 40g, 46d) in a novel, completely self-aligned configuration. The process of the invention permits higher packing densities, and allows feature distances to approach 0.5 μm and lower. A unique combination of masks in conjunction with a multi-layer structure (28) formed on the surface of a semiconductor wafer (16), the multi-layer structure including a buried etch-stop layer therein (28b), defines the source (18), gate (22), and drain (20) elements and their geometry relative to each other and to interconnects. Polysilicon plug (40, 46) contacts through slots in the multi-structure layer permit vertical contact to be made to the various elements. Silicidation (56) of the polysilicon plugs reduces series resistance in the vertical direction and permits strapping of N + and p + polysilicon plugs.

What is claimed is: 
     
       1. An improved interconnect for an array of field effect transistors formed in a major surface of a semiconductor substrate, said transistors comprising source, gate, and drain regions and corresponding contacts thereto, said contacts isolated from each other by an insulating layer, with conducting interconnects making contact to said contacts, thereby interconnecting said array of field effect transistors, wherein said contacts terminate in an upper surface that is coplanar with the upper surface of said insulating layer, wherein said insulating layer comprises a planarized multilayer structure comprising: (a) a first layer consisting essentially of an oxide;   (b) a second layer consisting essentially of an etch-stop material having a significantly different etch rate than the oxide of said first layer; and   (c) a third layer consisting essentially of an oxide, and wherein said interconnects to said contacts are formed at the same layer on said third oxide layer for all transistors to provide improved packing density and coplanar connections between transistors.   
     
     
       2. The interconnect of claim 1 comprising polysilicon or tungsten. 
     
     
       3. The interconnect of claim 2 wherein said polysilicon comprises undoped polysilicon, n-doped polysilicon, or p-doped polysilicon. 
     
     
       4. The interconnect of claim 3 comprising silicided polysilicon. 
     
     
       5. The interconnect of claim 1, wherein said insulating layer has an outer surface which is planar and substantially parallel to said semiconductor substrate, said interconnect formed on said planar insulating layer to comprise a planarized interconnect. 
     
     
       6. The interconnect of claim 1 wherein said semiconductor substrate comprises silicon, said first layer consists essentially of silicon dioxide, said second layer consists essentially of silicon nitride, and said third layer consists essentially of silicon dioxide. 
     
     
       7. The interconnect of claim 6 wherein said first layer of silicon dioxide is about 2,500 Å thick. 
     
     
       8. The interconnect of claim 6 wherein said first layer of silicon dioxide is about 400 Å thick. 
     
     
       9. The interconnect of claim 1 wherein said interconnects are all formed on said first oxide layer. 
     
     
       10. An improved interconnect for an array of CMOS devices formed in a major surface of a semiconductor substrate, said CMOS devices comprising source, gate, and drain regions and corresponding contacts thereto, said contacts isolated from each other by an insulating layer, with conducting interconnects making contact to said contacts, thereby interconnecting said array of field effect transistors, wherein said contacts terminate in an upper surface that is coplanar with the upper surface of said insulating layer, wherein said insulating layer comprises a planarized multilayer structure comprising: (a) a first layer consisting essentially of an oxide;   (b) a second layer consisting essentially of an etch-stop material having a significantly different etch rate than said first oxide layer; and   (c) a third layer consisting essentially of an oxide, and (3) wherein said interconnects to said contacts are formed at the same layer on said third layer for all transistors to provide improved packing density and coplanar connections between transistors.   
     
     
       11. The interconnect of claim 10 wherein said conducting interconnects comprise undoped polysilicon, n-doped polysilicon, or p-doped polysilicon. 
     
     
       12. The interconnect of claim 11 comprising silicided polysilicon. 
     
     
       13. The interconnect of claim 10 wherein said insulating layer has an outer surface which is planar and substantially parallel to said semiconductor substrate, said interconnect formed on said planar insulating layer to comprise a planarized interconnect. 
     
     
       14. The interconnect of claim 10 wherein said semiconductor substrate comprises silicon, said first layer consists essentially of silicon dioxide, said second layer consists essentially of silicon nitride, and said third layer consists essentially of silicon dioxide. 
     
     
       15. The interconnect of claim 14 wherein said first layer of silicon dioxide is about 2,500 Å thick. 
     
     
       16. The interconnect of claim 14 wherein said first layer of silicon dioxide is about 400 Å thick. 
     
     
       17. The interconnect of claim 10 whererin said interconnects are all formed on said first oxide layer.