Method and device for the asynchronous transmission of data by packets

Abstract

A method and device are provided for the asynchronous transmission of data packets, consisting in transmitting messages in the asynchronous mode, the messages comprising a beginning of message character, a character designating the address of the addressee, possibly a character designating the address of the sender, possibly characters containing the significant information of the message, and an end of message character. The beginning of message and end of message characters are formed of a continuous pulse of a length equal to the number of the significant bits of a normal message character increased by two bits. Such a pulse is recognized by the frame control circuits, in the case where the characters are without parity bits; they are recognized by the parity control signals in the case where the characters are provided with parity bits.

What is claimed is: 
     
       1. A method for use in a device for multipoint type of asynchronous series communication of logic messages between several transceivers connected in parallel to a network, the messages being formed of a succession of bits, without incorporated clock, grouped in coded characters separated by intervals, each character comprising a beginning of character bit and an end of character bit, the messages comprising a beginning of message character, at least one character designating the address of an addressee, one or more optional characters designating the address of a sender, optional significant characters, and an end of message character, the method comprising a first reception phase during which the sender listens to the signals which may be present on the network and generates an inhibition order which inhibits transmission as long as a signal is present, a second transmission phase during which the sender transmits a message and proceeds with the simultaneous reception of the signals and characters present in the network, comparison between the received signals and the transmitted signals, and interruption of the transmission of the message if the received signals and the transmitted signals differ, the interrupted transmission being begun again subsequently after a new initial reception phase of random duration, wherein: when the received signals and the transmitted signals differ, the sender inhibits the transmission of the message so that it transmits no bit over the network after the inhibition order; and   the beginning of message and end of message characters comprise a continuous pulse whose duration is equal to the duration of the whole of the significant bits forming an intermediate character of the messages increased by the duration of two bits.   
     
     
       2. The method as claimed in claim 3, wherein: the current intermediate characters of the messages comprise a beginning of character bit at logic state 0, n significant bits, and an end of character bit at logic state 1, in accordance with the usual asynchronous character transmission standards,   the beginning and end of message characters are formed of a continuous pulse, at logic state 0, whose duration is equal to the total duration of a character, including the beginning of character and end of character bits,   the character received is interpreted by a transceiver as being a beginning of message or end of message character when the receiver ascertains that this character has a frame error and that all its significant bits are at logic state 0.   
     
     
       3. The method as claimed in claim 1, wherein: the current intermediate characters of the messages comprise a beginning of character bit, n significant bits, an odd parity bit, an end of character bit, in accordance with the usual asynchronous character transmission standards,   the beginning and end of message characters are pulses formed of a n significant bits at logic state 0, with a parity bit at logic state 0;   the beginning of message and end of message characters are detected, in the receiver, when the receiver ascertains that this character has a parity error and that all its significant bits are at logic state 0.   
     
     
       4. The method as claimed in claim 1, wherein: the current intermediate characters of the messages comprise a beginning of character bit, n significant bits in even number, an even parity bit, an end of character bit, in accordance with the usual asynchronous character transmission standards,   the beginning and end of message characters are pulses formed of a n significant bits at logic state 1, with a parity bit at logic state 1;   the beginning of message and end of message characters are detected, in the receiver, when the receiver ascertains that this character has a parity error and that all its significant bits are at logic state 1.   
     
     
       5. A method for use in a device for multipoint type of asynchronous series communication of logic messages between several transceivers connected in parallel to a network, the messages being formed of a succession of bits, without incorporated clock, grouped in coded characters separated by intervals, each character comprising a beginning of character bit and an end of character bit, the messages comprising a beginning of message character, at least one character designating the address of an addressee, one or more optional characters designating the address of a sender, optional significant characters, and an end of message character, the method comprising a first reception phase during which the sender listens to the signals which may be present on the network and generates an inhibition order which inhibits transmission as long as a signal is present, a second transmission phase during which the sender transmits a message and proceeds with the simultaneous reception of the signals and characters present in the network, comparison between the received signals and the transmitted signals, and interruption of the transmission of the message if the received signals and the transmitted signals differ, the interrupted transmission being begun again subsequently after a new initial reception phase of random duration, wherein: when the received signals and the transmitted signals differ, the sender inhibits the transmission of the message so that it transmits no character over the network after the inhibition order; and   the random duration, which a sender must wait before transmitting a message after the last signal received over the network, is modified as a function of the message to be transmitted.   
     
     
       6. The method as claimed in claim 5, wherein at least two distinct variation ranges are defined, without overlapping, for the random transmission waiting time after reception of the last signal received. 
     
     
       7. A device for the asynchronous series communication, of multipoint type, of logic messages between several transceivers connected in parallel to a network, each transceiver comprising: means for storing each character forming the message to be transmitted, means for transmitting in series the bits forming the messages, means for receiving and storing the signals received over the network, means for generating the characters designating the address of the sender(s) and that of the addressee, means for comparing the signals corresponding to the message to be transmitted and the signals corresponding to the message received simultaneously by the reception means, means for inhibiting the transmission for a random time if the signals present and transmitted differ,   means for organizing the messages into a succession of bits grouped into coded characters, without incorporated clock, each character transmitted comprising a set of significant bits preceded by a beginning of character bit and followed by an end of character bit,   timing means for producing inhibition of the transmission for a random time greater than a predetermined waiting time following reception of a preceding signal,   means for generating in the transmitter a beginning of message character and means in the receiver for detecting the beginning of message character,   means for generating in the transmitter an end of message character and means for detecting in the receiver the end of message character,   means for conditioning, in the transmitter, the messages into a succession of characters with a beginning of message character, intermediate characters, and an end of message character,   means for deconditioning the messages in the receiver and extracting the intermediate characters, wherein:   the means for producing a beginning of message character are formed by the means themselves generating the intermediate characters of the messages, these means generating a character of the same duration as a current intermediate character, comprising a continuous pulse whose duration is equal to the duration of the set of significant bits forming an intermediate character of the messages, increased by the duration of two bits.   
     
     
       8. The device as claimed in claim 7, wherein the receivers of the device comprise: frame control means for analyzing each character received, and producing frame errors signals,   means for analyzing the character received for producing an enabling signal when all the significant bits of the character received are at logic state 0,   processing means receiving the frame error signals and the enabling signals and producing a signal of reception of a beginning of message or end of message character when a frame error signal and an enabling signal are present simultaneously for the character received.   
     
     
       9. The device as claimed in claim 7, wherein the receivers of the device comprise: odd parity control means for analyzing each character received and producing odd parity error signals,   means for analyzing the character received for producing an enabling signal when all the significant bits of the character received are at logic state 0,   processing means receiving the odd parity error signals and the enabling signals and producing a signal of reception of a beginning of message or end of message character when an odd parity error signal and an enabling signal are present simultaneously for the character received.   
     
     
       10. The device as claimed in claim 7, wherein the receivers of the device comprise: even parity control means for analyzing each character received and producing even parity error signals,   means for analyzing the character received for producing an enabling signal when all the significant bits of the character received are at logic state 1,   processing means receiving the even parity error signals and the enabling signals and producing a signal of reception of a beginning of message or end of message character when an even parity error signal and an enabling signal are present simultaneously for the character received.   
     
     
       11. A device for the asynchronous series communication, of multipoint type, of logic messages between several transceivers connected in parallel to a network, each transceiver comprising: means for storing each character forming the message to be transmitted, means for transmitting in series the bits forming the messages, means for receiving and storing the signals received over the network, means for generating the characters designating the address of the sender(s) and that of the addressee, means for comparing the signals corresponding to the message to be transmitted and the signals corresponding to the message received simultaneously by the reception means, means for inhibiting the transmission for a random time if the signals present and transmitted differ,   means for organizing the messages into a succession of bits grouped into coded characters, without incorporated clock, each character transmitted comprising a set of significant bits preceded by a beginning of character bit and followed by an end of character bit,   timing means for producing inhibition of the transmission for a random time greater than a predetermined waiting time following reception of a preceding signal,   means for generating in the transmitter a beginning of message character and means in the receiver for detecting the beginning of message character,   means for generating in the transmitter an end of message character and means for detecting in the receiver the end of message character,   means for conditioning, in the transmitter, the messages into a succession of characters with a beginning of message character, intermediate characters, and an end of message character,   means for conditioning the messages in the receiver and extracting the intermediate characters, wherein:   the means for producing an end of message character are formed by the means themselves generating the intermediate characters of the messages, these means generating a character of the same duration as a current intermediate character, comprising a continuous pulse whose duration is equal to the duration of the set of significant bits forming an intermediate character of the messages, increased by the duration of two bits.