Hybrid interconnection structure

Abstract

A hybrid interconnection structure is disclosed having application to the fine pitch interconnection of delicate semiconductor chips. The invention entails the use of a beam lead interconnect in which patterned conductor runs are provided on the upper surface of a silicon chip. The conductor runs extend beyond the chip to form a paired set of beam leads. One set of beam leads makes contact with terminals on the upper surface of one chip and the other set of beam leads makes contact with terminals on the upper surface of another chip. The interconnect chip is set on a substrate common to the interconnected chips with its top surface slightly (normally less than 1-2 mils) above the top surfaces of the interconnected chips. This limits any downward deformation of the beam leads in the bonding process to insure reliability of the bond for fine pitch application. The invention has specific application to arrays of infrared detectors in which interconnections are provided between a delicate light sensing chip of mercury cadmium telluride or indium antimonide and more rugged readout integrated circuits, usually of silicon.

What is claimed is: 
     
       1. A hybrid interconnection structure comprising in combination: (A) a substrate;   (B) a first semiconductor chip having its undersurface supported upon said substrate, and having on its upper surface an integrated circuit and near an edge of said upper surface a first plurality of closely spaced terminals;   (C) a second semiconductor chip having its undersurface supported upon said substrate at a position spaced from said chip and having on its upper surface an integrated circuit and near an edge of said upper surface a second plurality of closely spaced terminals oriented for sequential connection to said first plurality of terminals; and   (D) a beam lead interconnect comprising a third chip of semiconductor material having its undersurface supported upon said substrate and having on its upper surface a plurality of patterned conductor runs maintained in rigid, mutually spaced relation, each conductor run extending beyond the edges of said third chip to form a first and a second beam lead of sufficient length for bonding to a terminal on an adjacent chip,   said interconnect being supported upon said substrate at a position between said first and second chips with said beam leads and terminals in registration and in mutually bonded condition to sequentially interconnect said first and second pluralities of terminals.   
     
     
       2. The hybrid interconnection structure set forth in claim 1 wherein (1) at least one of said first and second chips contains active circutiry, and   (2) said third chip contains only passive circuitry, said interconnect providing fine pitch interconnections between said first and second chips.   
     
     
       3. The hybrid interconnection structure set forth in claim 1 wherein (1) one of said first and second chips is an array of optical detectors, and the other of said first and second chips is a readout circuit, and   (2) the pitch of said interconnections lie in the range of a fraction of a mil to several mils.   
     
     
       4. The hybrid interconnection structure set forth in claim 2, wherein the material of said third chip is silicon, having its upper surface slightly elevated above the upper surfaces of said first and second chips to limit downward deformation of said beam leads in forming bonds, and   said beam leads are gold, processed for ductility to facilitate said deformation and enhance the reliability of said bonds when formed with minimum mechanical stress.   
     
     
       5. The hybrid interconnection structure set forth in claim 2 wherein said beam leads are of a thickness of approximately 0.2 mil, a length of approximately 7 to 10 mils and a downward deformation when bonded, limited to less than two mils.   
     
     
       6. The hybrid interconnection structure set forth in claim 4 wherein said beam leads have an underlying soft metallic layer to enhance the reliability of said bonds where formed with minimum mechanical stress.   
     
     
       7. The hybrid interconnection structure set forth in claim 6 wherein said soft metallic layer is indium.   
     
     
       8. The hybrid interconnection structure set forth in claim 6 wherein at least one said first and second chips is of a fragile semiconductor material.   
     
     
       9. The hybrid interconnection structure set forth in claim 8 wherein said fragile material is a semiconductor of the class including GaAs, InSb, and HgCdTe.   
     
     
       10. The hybrid interconnection structure set forth in claim 8, wherein said beam leads are bonded with non-vibratory, low pressure, pulsed thermal compression bonds to limit the temperature rise and thermal and mechanical stresses upon the underlying chips during bonding.   
     
     
       11. The hybrid interconnection structure set forth in claim 6 wherein said patterned conductor runs and beam leads of said third chip are formed from a metallization of the upper surface of an extended silicon member, the edges of said member being chemically removed to form said chip, the portions of said metallization overhanging said chip forming self suppporting beam leads.   
     
     
       12. A hybrid interconnection structure as set forth in claim 2 wherein said structure forms the focal plane of a charge transfer device camera,   said integrated circuit on said first chip is an optical array of photo sensors, and   the integrated circuit on said second chip is a readout circuit for connection to said optical array.   
     
     
       13. A hybrid interconnection structure as set forth in claim 12 wherein said first chip is an optically sensitive semiconductor material of the class including InSb and HgCdTe.   
     
     
       14. A hybrid interconnection structure as set forth in claim 12 wherein said integrated circuit is a linear time delay integration optical array.