Delta-sigma modulator with oscillation detect and reset circuit

Abstract

An oscillation detect and reset circuit is provided for an analog modulator that includes a first stage of integration having a single ended differential amplifier (32) which is connected to the input of three stages of subsequent integration (40), (42) and (44), in a cascaded configuration. The output of the last stage of integration (44) is connected to the input of a one-bit quantizer (48). The output of the one-bit quantizer (48) is connected to the input of a current (50) feedback, which is connected between a summing node (36) and a negative voltage supply. The summing node (36) sums the current feedback with an input voltage for input to the amplifier (32). Switches (52), (54) and (56) are provided across the inputs and outputs of the integration stages (40), (42) and (44), respectively. The sensing of an unstable condition on the output of second stage of integration (40) is detected by oscillation detect comparators (60) and (62) to initiate a count cycle in a five-bit counter (66). The output of counter (66) generates a oscillation detect signal upon detection of an oscillation, which signal is output to the control inputs of the switches (52), (54) and (56), for thirty-two cycles of the analog modulator sampling frequency. This is a sufficient amount of time to allow the loop, which is a first order loop, to zero out during the reset period.

What is claimed is: 
     
       1. An instability detect/correction circuit for an analog modulator in an analog-to-digital converter, the analog modulator having at least two cascaded filter sections, the detect/correction circuit comprising: a comparator circuit for comparing the operating characteristics of the modulator with a predetermined reference to determine if the analog modulator is operating at or near an unstable condition;   at least one zeroing circuit disposed on at least one of the filter sections and operable to substantially zero the associated filter section to remove accumulated information therefrom, said zeroing circuit operating in response to generation of an instability detection signal; and   a control circuit for generating said instability detection signal for a predetermined amount of time in response to said comparator circuit determining that the modulator is operating at or near an unstable condition.   
     
     
       2. The detect/correction circuit of claim 1 wherein each of said filter sections include an integrator, and said comparator circuit measures the output level of one of the integrators and compares it with said predetermined stability reference and, if said measured output exceeds said predetermined stability reference, a true comparison signal is generated by said comparator, said true comparison signal indicating that the modulator is operating at or near an unstable condition. 
     
     
       3. The detect/correction circuit of claim 1 wherein said unstable condition comprises oscillation of the modulator. 
     
     
       4. The detect/correction circuit of claim 1 wherein said comparator circuit is operable to determine only if the modulator is operating in an unstable condition. 
     
     
       5. The detection/correction circuit of claim 1 wherein at least one of the filter sections includes an integrator and said zeroing circuit comprises a switch being disposed between the input and the output of said integrator, said switch being closed in response to the generation of said instability detection signal. 
     
     
       6. The detect/correction circuit of claim 5 wherein each of the filter sections includes an integrator, each integrator having a switch disposed between the input and output thereof and operable to be closed in response to generation of said instability detection signal. 
     
     
       7. The detect/correction circuit of claim 1 wherein said zeroing circuit is disposed on all of said filter sections not including the first filter section, with the first filter section allowed to operate when said zeroing circuits are operating in response to generation of said instability detection signal, such that the first filter section operates during the zeroing operation to form a first order loop. 
     
     
       8. The detect/correction circuit of claim 7 wherein the predetermined amount of time during which said control circuit generates said instability detection signal is sufficient to allow the first filter section to reach a stable operating condition. 
     
     
       9. An instability detect/correction circuit for an analog modulator, the analog modulator having at least two cascaded filter sections, the detect/correction circuit comprising: a switch disposed between the input and output of all of the cascaded filter sections with the exception of the first filter section, said switch operable to be in a closed position in response to the presence of an instability detect signal, the switch operable to substantially zero the associated one of the filter sections to remove accumulated information therefrom;   an instability detect circuit of detecting whether the modulator is operating at or near an unstable condition whereupon said instability detect signal is generated; and   a timer for maintaining the presence of said instability detect signal for a predetermined amount of time to allow said first filter section to reach a stable operating condition.   
     
     
       10. The detect/correction circuit of claim 9 wherein said instability detection circuit is comprised of a comparator for comparing the output of at least the second of the integration stages with a predetermined stability threshold and generating said instability detect signal when the output of the measured one of the cascaded filter sections exceeds said stability threshold. 
     
     
       11. The detect/correction circuit of claim 9 wherein the analog modulator includes a plurality of cascaded filter sections with said switches being disposed on all of said filter sections with the exception of the first filter section. 
     
     
       12. A detection/correction method for detecting instabilities in an analog modulator and correcting these instabilities, the analog modulator having at least two cascaded filter sections, the method comprising the steps of: monitoring the operating characteristics of the analog modulator;   comparing the operating characteristics of the analog modulator with a predetermined stability reference to determine if the modulator is operating at or near an unstable condition as defined by the predetermined stability reference;   generating an instability detect signal for a predetermined amount of time when it is determined that the analog modulator is operating at or near an unstable condition; and   controlling at least one of the filter sections to substantially zero the filter section to remove accumulated information therefrom in response to the presence of the instability detect signal.   
     
     
       13. The method of claim 12 wherein the step of determining if the modulator is operating at or near an unstable condition comprises: measuring the output level of one of the filter sections;   comparing the output level of the measured filter sections with said predetermined stability reference; and   generating the instability detect signal when the measured output of the measured one of the filter sections exceeds the predetermined stability reference.   
     
     
       14. The method of claim 12 wherein the filter sections each include an integrator and the step of zeroing the filter section comprises: disposing a switch on at least one of the integrators between the input and the output thereof and normally in an open position; and   closing the switch when the instability detect signal is generated.   
     
     
       15. The method of claim 14 wherein a switch is disposed on all of the integrators between the input and the output thereof. 
     
     
       16. The method of claim 14 wherein a switch is disposed on all of the integrators except the integrator in the first filter section. 
     
     
       17. The method of claim 16 wherein the analog modulator operates as a first order modulator during the presence of the instability detect signal and the predetermined amount of time during which the instability detect signal is generated is sufficient to allow the first filter section to enter a stable operating region. 
     
     
       18. An instability detect/correction circuit for a convertor that converts an input digital or analog format signal to an output analog or digital format signal, respectively, representing the respective input digital or analog format signal, comprising: a comparator circuit for comparing the operating characteristics of the convertor with a predetermined reference to determine if the converter is operating at or near an unstable condition;   at least one zeroing circuit disposed on the converter and operable to substantially zero the converter to remove accumulated information therefrom, said zeroing circuit operating in response to generation of an instability detection signal; and   a control circuit for generating said instability detection signal for a predetermined amount of time in response to said comparator circuit determining that the converter is operating at or near an unstable condition.   
     
     
       19. The detection/correction circuit of claim 18 wherein the converter comprises a delta-sigma modulator. 
     
     
       20. The detection/correction circuit of claim 19 wherein said delta-sigma modulator is a digital delta-sigma modulator. 
     
     
       21. The detection/correction circuit of claim 17 wherein said delta-sigma modulator comprises an analog delta-sigma modulator. 
     
     
       22. An instability detection/correction circuit for an digital modulator in a digital-to-analog converter, the digital modulator having at least two cascaded filter sections, the detection/correction circuit comprising: a comparator circuit for comparing the operating characteristics of the modulator with a predetermined reference to determine if the digital modulator is operating at or near an unstable condition;   at least one zeroing circuit disposed on at least one of the filter sections and operable to substantially zero the associated filter section to remove accumulated information therefrom, said zeroing circuit operating in response to generation of an instability detection signal; and   a control circuit for generating said instability detection signal for a predetermined amount of time in response to said comparator circuit determining that the modulator is operating at or near an unstable condition.   
     
     
       23. The detection/correction circuit of claim 22 wherein the filter sections each include an accumulator, and said comparator circuit measures the output level of one of the accumulators and compares it with said predetermined stability reference and, if said measured output exceeds said predetermined stability reference, a true comparison signal is generated by said comparator, said true comparison signal indicating that the modulator is operating at or near an unstable condition. 
     
     
       24. The detection/correction circuit of claim 22 wherein said unstable condition comprises oscillation of the modulator. 
     
     
       25. The detection/correction circuit of claim 22 wherein said comparator circuit is operable to determine only if the modulator is operating in an unstable condition. 
     
     
       26. The detection/correction circuit of claim 22 wherein at least one of the filter sections includes an accumulator and said zeroing circuit comprises a reset circuit for resetting the output of the integrator to zero in response to the generation of said instability detection signal. 
     
     
       27. The detect/correction circuit of claim 25 wherein each of the filter sections includes an accumulator, each accumulator having a reset circuit operable to be activated in response to generation of said instability detection signal. 
     
     
       28. The detection/correction circuit of claim 22 wherein said zeroing circuit is disposed on all of said filter sections after and not including the first filter section with the first filter section allowed to operate when said zeroing circuits are operating in response to generation of said instability detection signal, such that the first filter section operates during the zeroing operation to form a first order loop.