Method and circuit for scanning capacitive loads

Abstract

A high-speed scanning method uses a K(K≧3)-number of semiconductor switch elements each having a first main electrode responsive to an input signal, a second main electrode, and a control electrode responsive to a control signal for controlling the transmissive and intransmissive states of said input signal from the first main electrode to the second main electrode; and capacitive loads connected respectively with the second main electrode of each of said K-number of semiconductor switch elements, for shifting one of the K-number of semiconductor switch elements sequentially with a predetermined period from the transmissive state to the intransmissive state or vice versa, wherein, the time, for which an arbitary L(K>L≧2)-number of semiconductor switch elements of adjacent scans are rendered transmissive, and the time, for which the L-number of semiconductor switch elements are rendered intransmissive, are included in at least one frame period, to elongate the period for which the scanning signals fluctuate, thereby permitting use of low-frequency semiconductor switches.

What is claimed is: 
     
       1. A signal circuit for feeding display data signals to a display, comprising: an input line receiving display data signals;   a signal input sampling circuit connected to said input terminal and comprising, a first control circuit producing a first plurality of control signals;   a first switching circuit, said first switching circuit being responsive to said first plurality of control signals;   a second control circuit producing a second plurality of control signals;   a second switching circuit, coupled to said first switching circuit and having a plurality of output lines, wherein said display data signals appear at ones of said plurality of output lines in accordance with a timing defined by said first plurality of control signals and said second plurality of control signals;     a hold circuit coupled to each of said plurality of output lines;   a data transfer circuit connected to each of said plurality of output lines; and   a display unit driver coupled to said data transfer circuit, wherein said first switching circuit comprises n switching devices, where n is an integer ≧2 and wherein,     each switching device has an input terminal, an output terminal and a control terminal;   the input terminal of each of said n switching devices is coupled to said input line;   the control terminal of each of said n switching devices is coupled to said first control circuit and receives one of said first plurality of control signals that is associated with the given one of said n switching devices; and   the display data signals appear at the output terminals of said n switching devices with a timing defined by said first plurality of control signals,   wherein said second switching circuit comprises m switching devices, where m is an integer and is defined by s×n, where s is an integer ≧1,   each of said m switching devices having an input terminal, an output terminal and a control terminal,   said input terminal of each of said m switching devices is coupled to an output terminal of an associated one of said n switching devices,   said output terminal of each of said m switching devices is coupled to said holding circuit and said data transfer circuit, and   said control terminal of each of said m switching devices is coupled to said second control circuit and receives one of said second plurality of control signals that is associated with the given one of said m switching devices,   wherein at least two of said n switching devices are on at the same time as controlled by said first plurality of control signals and at least two of said m switching devices are on at the same time as controlled by said second plurality of control signals.   
     
     
       2. The signal circuit of claim 1 wherein said holding circuit comprises a plurality of capacitive loads, where a capacitive load is associated with each of said m plurality of switching devices. 
     
     
       3. The signal circuit of claim 1 wherein said data transfer circuit comprises a third plurality of further switching devices, wherein said third plurality comprises m further switching devices, one for each of said m switching devices of said second switching circuit. 
     
     
       4. The signal circuit of claim 1 wherein all of said m and n switching devices comprise thin film transistors. 
     
     
       5. The signal circuit of claim 3 wherein all of said m and n switching devices, and said m further switching devices comprise thin film transistors. 
     
     
       6. A signal circuit for feeding display data signals to a display, comprising: an input line receiving display data signals;   a signal input sampling circuit connected to said input terminal and comprising, a first control circuit producing a first plurality of control signals;   a first switching circuit, said first switching circuit being responsive to said first plurality of control signals;   a second control circuit producing a second plurality of control signals;   a second switching circuit, coupled to said first switching circuit and having a plurality of output lines, wherein said display data signals appear at ones of said plurality of output lines in accordance with a timing defined by said first plurality of control signals and said second plurality of control signals;     a hold circuit coupled to each of said plurality of output lines;   a data transfer circuit connected to each of said plurality of output lines; and   a display unit driver coupled to said data transfer circuit;   wherein said first switching circuit comprises n sets of y switching transistors where n and y are integers ≧2 and wherein, each switching device has an input terminal, an output terminal, and a control terminal;   the control terminal of each of said y switching devices of one of said n sets of switching devices is coupled to said first control circuit to receive the same one of said first plurality of control signals associated with that set of switching devices;   the input terminal of each of the n×y switching devices is coupled to said input line; and   the display data signals appear at the output terminals of said n×y switching devices with a timing defined by said first plurality of control signals.     
     
     
       7. The signal circuit of claim 6 wherein said second switching circuit comprises m switching devices, where m is an integer and is defined by s×n×y, where s is an integer ≧1, each of said m switching devices having an input terminal, an output terminal and a control terminal;   said input terminal of each of said m switching devices is coupled to an output terminal of an associated one of said n×y switching devices;   said output terminal of each of said m switching devices is coupled to said holding circuit and said data transfer circuit, and   said control terminal of each of said m switching devices is coupled to said second control circuit and receives one of said second plurality of control signals that is associated with a given one of said m switching devices.   
     
     
       8. The signal circuit of claim 7 wherein said holding circuit comprises a plurality of capacitive loads, where a capacitive load is associated with each of said m plurality of switching devices. 
     
     
       9. The signal circuit of claim 7 wherein said data transfer circuit comprises a third plurality of further switching devices, wherein said third plurality comprises m further switching devices, one for each of said m switching devices of said second switching circuit. 
     
     
       10. The signal circuit of claim 7 wherein all of said m and n switching devices comprise thin film transistors. 
     
     
       11. The signal circuit of claim 9 wherein all of said m and n switching devices, and said m further switching device comprise thin film transistors. 
     
     
       12. An input signal sampling circuit in a driving circuit for displaying data signals, comprising: an input line;   a first control circuit producing 1 control signals where 1 is an integer ≧2;   a first switching circuit coupled to said input line and said first control circuit and receiving said 1 control signals, said first switching circuit further including a plurality of output lines;   a second control circuit producing a plurality of second control signals; and   a second switching circuit, coupled to said second control circuit and said plurality of output lines of said first switching circuit, wherein said first switching circuit comprises 1 sets of switching devices where each of said 1 sets includes n switching devices where n is an integer >1, such that the total number of switching devices in said first switching circuit is n×1;     each of said n×1 switching devices has an input terminal coupled to said input line, a control terminal coupled to said first control circuit, and an output terminal coupled to said second switching circuit such that each of said 1 sets of switching devices is associated with one of said 1 first control signals;   wherein said second switching circuit comprises m switching devices where m is an integer defined by s×n×1 where s is an integer >1 and wherein each of said m switching devices comprises an input terminal coupled to an output terminal of one of said n×1 switching devices;   wherein said second control circuit produces at least n control signals each being supplied to different ones of said m switching devices; and   wherein at least two of said n control signals have a first value at the same time, wherein when the said first value is applied to a control terminal of one of said m switching devices, said one switching device passes a signal on its input terminal to its output terminal.