N-channel clamp for ESD protection in self-aligned silicided CMOS process

Abstract

An ESD protection device is formed in an integrated circuit by an N-channel grounded-gate transistor. This protection device has a polysilicon gate, just as other P- and N-channel transistors in the integrated circuit device, but the siliciding of the protection device is controlled so that adverse effects of ESD events are minimized. There are no silicide areas created on top of the polysilicon gate of the protection device, nor on the source/drain regions near the gate and self-aligned with the gate, as there is for other transistors made by the CMOS process. The siliciding of the protection transistor near the gate is prevented by using a deposited oxide layer as a mask, and this oxide layer is also used to create sidewall spacers for the transistor gates. The sidewall spacers are used in creating self-aligned silicided areas over the source/drain regions, self-aligned with the gates, for all P- and N-channel transistors except the protection transistors. A standard process for making CMOS integrated circuits having self-aligned silicided source/drain areas may be used, with the addition of only one non-critical masking step to block the siliciding of protection transistors.

What is claimed is: 
     
       1. An integrated circuit device comprising: (a) at least one transistor having source/drain regions formed in a face of a semiconductor body and having a gate on said face;   (b) sidewall spacers on sidewalls of said gate and formed of a deposited oxide;   (c) said transistor having source and drain regions in said face and having silicided areas of said face on said source and drain regions, said silicided areas being self-aligned with said sidewall spacers;   (d) an ESD protection device at said face, said protection device including a gate and including source and drain regions of the same type as said source/drain regions of said transistor, and a masking layer of said deposited oxide over said gate and over said source and drain regions adjacent said gate of said protection device, said ESD protection device not having silicided areas at said face on said gate or on said source and drain regions adjacent said gate.   
     
     
       2. An integrated circuit device according to claim 1 wherein said at least one transistor includes at least one N-channel MOS transistor and at least one P-channel MOS transistor. 
     
     
       3. An integrated circuit device according to claim 1 wherein said source and drain regions of said ESD protection device are N-type and formed in a P-type semiconductor body. 
     
     
       4. An integrated circuit device according to claim 3 wherein said integrated circuit device includes both P-channel and N-channel MOS transistors formed at said face. 
     
     
       5. An integrated circuit device according to claim 1 wherein said ESD protection device has silicided areas on said source and drain regions, said silicided areas being spaced from said gate by a distance greater than the width of said gate of said ESD protection device. 
     
     
       6. An integrated circuit device according to claim 5 including metal-to-silicide contacts to said silicided areas of said source and drain regions of said ESD protection device. 
     
     
       7. An output buffer having electrostatic protection and formed as an integrated circuit device, comprising: (a) an N-channel pull-down transistor having a source-to-drain path and a P-channel pull-up transistor having a source-to-drain path, said source-to-drain paths of said transistors being connected in series and the series source-to-drain paths being connected across a voltage supply, the voltage supply having a reference terminal and a voltage terminal;   (b) an output pad connected to a juncture of said series source-to-drain paths of said transistors;   (c) a N-channel protection transistor having a source-to-drain path, said source-to-drain path of said protection transistor being connected between said output pad and said reference terminal of said voltage supply and having a gate connected to said reference terminal;   (d) said pull-up transistor having a silicided polysilicon gate and having self-aligned silicided areas on source and drain regions closely adjacent said silicided polysilicon gate but spaced therefrom by sidewall spacers; and said pull-down transistor having a silicided polysilicon gate and having self-aligned silicided areas on source and drain regions closely adjacent said silicided polysilicon gate but spaced therefrom by sidewall spacers;   (e) said protection transistor having a non-silicided polysilicon gate and having source and drain regions with no self-aligned silicide thereon.   
     
     
       8. A device according to claim 7 wherein said source and drain regions of said protection transistor have non-self-aligned silicide areas thereon spaced from said non-silicided polysilicon gate of said protection transistor by greater than the width of said polysilicon gate of said protection transistor. 
     
     
       9. A device according to claim 7 wherein said output pad is connected to said juncture by resistive means.