US5021897AExpiredUtility

Memory system for recording and reproducing block unit data

47
Assignee: MATSUSHITA ELECTRIC INDUSTRIAL CO LTDPriority: Jun 12, 1987Filed: Jun 7, 1988Granted: Jun 4, 1991
Est. expiryJun 12, 2007(expired)· nominal 20-yr term from priority
H04N 9/802G11B 20/10527G11B 2220/90G11B 20/1208G11B 27/3027G11B 20/1833G11B 20/1211G11B 2220/913G11B 20/1809H04N 5/935G11B 20/10
47
PatentIndex Score
10
Cited by
10
References
1
Claims

Abstract

There is provided a signal processing system for recording and reproducing a video signal and a digital audio signal with a rotary-head VTR and, more particularly, a memory control system which generates a block address and a memory write signal so that the sync signal for reproduced digital data is detected reliably and the digital data is stored in the memory circuit correctly.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. A signal processing system for controlling recording and reproduction of block unit data which is adapted to be recorded at a predetermined position on a track of a magnetic tape and which includes digital data representing an information signal, a synchronizing signal and an address code indicative of an address value of a block unit in which said digital data is contained, said signal processing system comprising: address predicting means for predicting said address code in accordance with a rotational position of a rotary head which reproduces data recorded on the magnetic tape; reading means for reading said address code; address generation means for generating said address value in accordance with said sync signal; composed address value generation means for generating a composed address value on the basis of an output of said reading means and an output of said address generation means; first address value comparison means for comparing said composed address value with said predicted address code value; selection means for outputting said composed address value as an address value for accessing a memory circuit when a comparison error of said first address value comparison means is within a predetermined range; second address value comparison means for comparing the address value outputted from said selection means with said predicted address code value; and writing signal generation means for generating a writing signal for storing said digital data in said memory circuit when a comparison error of said second address value comparison means is within a predetermined range.

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