Serial bus interface capable of transferring data in different formats

Abstract

A serial bus interface includes a shift register for receiving and transmitting serial data, a first selector coupled to a serial input of the shift register selectively coupling the serial input of the shift register to either of two serial data lines, and a second selector coupled to a serial output of the shift register selectively coupling the serial output of the shift register to one of the two serial data lines. A clock generator, capable of generating a clock pulse in two different formats, is coupled to a clock line. The clock generator operates to output to the clock line a clock pulse in accordance with a format utilized by one of the serial data lines.

I claim: 
     
       1. A master processor for use in a serial data transfer system, the master processor being interconnected to at least first and second slave devices through the same single serial clock line, the master processor being interconnected to the first slave device through a first serial data line and the master processor being interconnected to the second slave device through a second serial data line, the master processor comprising: a shift register commonly receiving and transmitting serial data transferred from and to be transferred through the first and second serial data lines,   a first selector, coupled to a serial input of the shift register, capable of selectively coupling the serial input of the shift register to either one of the first and second serial data lines,   a second selector, coupled to a serial output of the shift register, capable of selectively coupling the serial output of the shift register to either one of the first and second serial data lines, and   a clock generator, coupled to the single serial clock line, capable of generating a clock pulse in at least two different transfer formats which are different from each other in the number of clock pulses to be supplied to the shift register, the clock generator operating to output to the single serial clock line a clock pulse in accordance with a format utilized by one of the first and second serial data lines selected by either the first selector or the second selector.   
     
     
       2. A master processor as claimed in claim 1 further including: a central processing unit (CPU) coupled to an internal bus of the master processor,   a format selection flag register located within the master processor and coupled to the internal bus and set by the CPU, and   a transmission/reception flag register located within the master processor and coupled to the internal bus and set by the CPU, and wherein   the first and second selectors are set in accordance with the contents of the format selection flag register and the transmission/reception flag register.   
     
     
       3. A master processor for use in a serial data transfer system, the master processor being interconnected to at least first and second slave devices through the same single serial clock line, the master processor being interconnected to the first slave device through a first serial data line and the master processor being interconnected to the second slave device through a second serial data line, the master processor comprising: a shift register receiving and transmitting serial data,   a first selector, coupled to a serial input of the shift register, capable of selectively coupling the serial input of the shift register to either one of the first and second serial data lines,   a second selector, coupled to a serial output of the shift register, capable of selectively coupling the serial output of the shift register to either one of the first and second serial data lines,   a clock generator, coupled to the single serial clock line, capable of generating a clock pulse in at least two different transfer formats which are different from each other in the number of clock pulses to be supplied to the shift register, the clock generator operating to output to the single serial clock line a clock pulse in accordance with a format utilized by one of the first and second serial data lines selected by either the first selector or the second selector,   a central processing unit (CPU) coupled to an internal bus of the master processor,   a format selection flag register located within the master processor and coupled to the internal bus and set by the CPU, and   a transmission/reception flag register located within the master processor and coupled to the internal bus and set by the CPU, and wherein   the first and second selectors are set in accordance with the contents of the format selection flag register and the transmission/reception flag register, the master processor further including   a clock control flag register, coupled to the internal bus and set by the CPU via the internal bus, and wherein the clock generator includes   a clock selector which generates a clock signal at a pulse rate capable of being varied by the CPU,   a NAND gate having a first input connected to receive the clock signal from the clock selector,   an AND gate connected at a third input to an output of the NAND gate and at a fourth input to the clock control flag register so as to output the clock signal to the clock terminal for a period in which the clock control flag register is set to "1",   a counter, connected to receive the clock signal, generating an interrupt request signal when the counter counts to a predetermined value, and   a flipflop having a set input connected to receive a set signal via the internal bus and a reset input connected to receive the interrupt request signal from the counter, and wherein   an output of the flipflop is connected to a second input of the NAND gate so that clock signals of a number corresponding to the predetermined value are outputted at a designated pulse rate from the clock terminal by setting the flipflop and setting the clock control flag register.   
     
     
       4. A master processor as claimed in claim 3 wherein the CPU discriminates a content of the format selection flag register when the interrupt request signal is generated, and when the format selection flag register indicates a first format, the CPU maintains a content of the clock control flag register unchanged, and when the format selection flag register indicates a second format, the CPU sequentially writes "0" and "1" into the clock control flag register so that an additional clock signal is generated from the AND gate. 
     
     
       5. A master processor for use in a serial data transfer system, the master processor being interconnected to at least first and second slave devices through the same single serial clock line, the master processor being interconnected to the first slave device through a first serial data line and the master processor being interconnected to the second slave device through a second serial data line, the master processor comprising: a shift register commonly receiving and transmitting serial data transferred from and to be transferred through the first and second serial data lines,   a selector, coupled to input terminals of the shift register, selectively coupling the shift register to either one of the first and second serial data lines, and   a clock generator, coupled to the single serial clock line, capable of generating a clock pulse in at least two different transfer formats which are different from each other in the number of clock pulses to be supplied to the shift register, the clock generator operating to output to the single serial clock line a clock pulse in accordance with a format utilized by one of the first and second serial data lines selected by the selector.   
     
     
       6. A serial data transfer system comprising: a first serial data line;   a second serial data line;   a single serial clock line;   a first slave station having a first data input/output terminal coupled to the first serial data line and a first clock terminal coupled to the single serial clock line;   a second slave station having a second data input/output terminal coupled to the second serial data line and a second clock terminal coupled to the single serial clock line; and   a master station having a first serial data input/output terminal coupled to the first serial data line, a second serial data input/output terminal coupled to the second serial data line, and a serial clock terminal coupled to the single serial clock line, the master station operating to supply to the single serial clock terminal a first number of clock signals when data is transferred between the master station and the first slave station, and a second number of clock signals, different in number from the first number of clock signals, when data is transferred between the master station and the second slave station, such that the master station can respectively communicate with the first and second slave stations in two different transfer formats which are different from each other in the number of clock pulses to be supplied.   
     
     
       7. A serial data transfer system comprising: a first serial data line;   a second serial data line;   a single serial clock line;   a first slave station having a first data input/output terminal coupled to the first serial data line and a first clock terminal coupled to the single serial clock line;   a second slave station having a second data input/output terminal coupled to the second serial data line and a second clock terminal coupled to the single serial clock line;   a master station including,   a shift register commonly receiving and transmitting serial data transferred from and to be transferred through the first and second serial data lines,   a selector, coupled to output terminals of the shift register, selectively coupling the shift register to either one of first and second serial data lines, and   a clock generator, coupled to the single serial clock line, capable of generating a clock pulse in at least two transfer formats which are different from each other in the number of clock pulses to be supplied to the shift register, the clock generator operating to output to the single serial clock line a clock pulse in accordance with a format utilized by one of the first and second serial data lines selected by the selector.   
     
     
       8. A master processor for use in a serial data transfer system, the master processor being interconnected to at least first and second slave devices through the same single serial clock line, the master processor being interconnected to the first slave device through a first serial data line and the master processor being interconnected to the second slave device through a second serial data line, the master processor comprising: a first data transfer terminal to be connected through the first serial data line to the first slave device;   a second data transfer terminal to be connected through the second serial data line to the second slave device;   a single serial clock terminal to be connected through the single serial clock line to the first slave device and to the second slave device;   a shift register temporarily holding data to be transferred and having a shift output terminal to shift and output temporarily held data, bit by bit, through said shift output terminal in synchronism with a shift clock pulse;   clock generating means for generating a clock pulse so as to supply a generated clock pulse to said clock terminal and also so as to supply said generated clock pulse to said shift register as said shift clock pulse;   a selector having an input connected to said shift output terminal, a first output connected to said first data transfer terminal, and a second output connected to said second data transfer terminal, said selector operating to connect said shift output terminal to said first data transfer terminal in a first data transfer mode, and operating to connect said shift output terminal to said second data transfer terminal in a second data transfer mode, the first and second data transfer modes being different from each other in the number of clock pulses to be supplied to the shift register;   detection means, coupled to said clock generating means, for generating a detection signal when a predetermined number of clock pulses has been generated by the clock generating means; and   control means, responding to the detection signal, for controlling said clock generating means so as to cause, in the first data transfer mode, the clock generating means to stop generating a clock pulse, and to cause in the second data transfer mode, the clock generating means to generate at least one additional clock pulse.   
     
     
       9. A master processor for use in a serial data transfer system, the master processor being interconnected to at least first and second slave devices through the same single serial clock line, the master processor being interconnected to the first slave device through a first serial data line and the master processor being interconnected to the second slave device through a second serial data line, the master processor comprising: a first data transfer terminal to be connected through the first serial data line to the first slave device;   a second data transfer terminal to be connected through the second serial data line to the second slave device;   a single serial clock terminal to be connected through the single serial clock line to the first slave device and to the second slave device;   a shift register temporarily holding received data and having a shift input terminal to shift and receive, bit by bit, data inputted to the shift input terminal in synchronism with a shift clock pulse;   clock generating means for generating a clock pulse so as to supply a generated clock pulse to said clock terminal and also so as to supply the generated clock pulse to the shift register as the shift clock pulse;   a selector having a first input connected to the first data transfer terminal, a second input connected to the second data transfer terminal, and an output connected to the shift input terminal, the selector operating to connect the first data transfer terminal to the shift input terminal in a first data transfer mode, and operating to connect the second data transfer terminal to the shift input terminal in a second data transfer mode the first and second data transfer modes being different from each other in the number of clock pulses to be supplied to the shift register;   detection means, coupled to the clock generating means, for generating a detection signal when a predetermined number of clock pulses has been generated by the clock generating means; and   control means, responding to the detection signal, for controlling the clock generating means so as to cause, in the first data transfer mode, the clock generating means to stop generating a clock pulse and to cause in the second data transfer mode, the clock generating means to generate at least one additional clock pulse.