By-pass boundary scan design

Abstract

The present invention implements self testable boundary logic by using a tristate pass gate and a tristate receiver in combination with a linear feedback shift register, a storage register, and level sensitive scan design (LSSD) techniques. The linear feedback shift register (LFSR) shifts data into a storage register which is connected to the data inputs of the boundary logic through the tristate pass gate. The outputs of the tristate input receiver are also connected to the inputs of the boundary logic so that the boundary logic can receive data from both the data input of the integrated circuit (data path) or from the storage register connected to the LFSR. The tristate pass gate and receiver are enabled through a self test signal such that when the pass gate is enabled the receiver is not enabled and vice versa. In this way the boundary logic can only get data from either the storage register or through the receiver but not both. In this configuration data from the storage register can be input into the boundary logic without going through a multiplexer in the data path and incurring the associated delay. The boundary logic can then be self tested using ordinary LSSD techniques. This self testing can also be performed with a minimum of additional silicon area being used for the self test structures.

We claim: 
     
       1. A self testable logic circuit comprising: a linear feedback shift register for generating test pattern scan information;   internal logic which receives test pattern scan information from said linear feedback shift register;   a multiple input shift register which receives scan information from said internal logic;   a tristate pass gate having inputs connected to outputs of said internal logic so as to receive test data from said internal logic;   input boundary logic having outputs connected to inputs of said internal logic;   a tristate receiver having outputs connected to inputs of said input boundary logic;   said tristate pass gate having outputs connected to inputs of said input boundary logic;   said tristate receiver outputs being enabled when a self test signal is in a first state, said tristate receiver outputs set to a high impedance state when said self test signal is in a second state;   said tristate pass gate outputs being enabled when said self test signal is in said second state, said tristate pass gate outputs set to a high impedance state when said self test signal is in said first state;   said input boundary logic receiving test pattern scan information from said linear feedback shift register through said internal logic and said tristate pass gate when said self test signal is in said second state;   said input boundary logic receiving data from said tristate receiver when said self test signal is in said first state; and   said scan information in said multiple input shift register indicates the functionality of said self testable logic circuit when said self test signal is in said second state.   
     
     
       2. A self testable logic circuit as in claim 1, further comprising: output boundary logic, a storage register, and an off chip driver;   said internal logic being connected to said output boundary logic and transmitting data to said output boundary logic;   said output boundary logic being connected to said storage register and said off chip driver;   said storage register being connected to said multiple input shift register;   said output boundary logic transmitting scan information to said multiple input shift register through said storage register when said self test signal is in said second state; and   said output boundary logic transmitting data to said off chip driver when said self test signal is in said first state.   
     
     
       3. A self testable logic circuit comprising: a linear feedback shift register for generating test pattern scan information;   internal logic which receives test pattern scan information rom said linear feedback shift register;   a multiple input shift register which receives scan information from said internal logic;   input boundary logic having outputs connected to inputs of said internal logic;   a tristate receiver having outputs connected to inputs of said input boundary logic;   a first storage register when receives test pattern scan information from said linear feedback shift register and sends said test pattern scan information to said multiple input shift register;   a tristate pass gate having inputs connected to outputs of said first storage register;   said tristate pass gate having outputs connected to inputs of said input boundary logic;   said tristate receiver outputs being enabled when a self test signal is in a first state, said tristate receiver outputs set to a high impedance state when said self test signal is in a second state;   said tristate pass gate outputs being enabled when said self test signal is in said second state, said tristate pass gate outputs set to a high impedance state when said self test signal is in said first state;   said input boundary logic receiving test pattern scan information from said linear feedback shift register through said first storage register and said tristate pass gate when said self test signal is in said second state;   said input boundary logic receiving data from said tristate receiver when said self test signal is in said first state; and   said scan information in said multiple input shift register indicates the functionality of said self testable logic circuit when said self test signal is in said second state.   
     
     
       4. A self testable logic circuit as in claim 3, further comprising: output boundary logic, a second storage register, and an off chip driver;   said internal logic being connected to said output boundary logic and transmitting data to said output boundary logic;   said output boundary logic being connected to said second storage register and said off chip driver;   said second storage register being connected to said multiple input shift register;   said output boundary logic transmitting scan information to said multiple input shift register through said second storage register when said self test signal is in said second state; and   said output boundary logic transmitting data to said off chip driver when said self test signal is in said first state.   
     
     
       5. A method of testing self testable logic circuits comprising: generating test pattern scan information in a linear feedback shift register;   applying said test pattern scan information to internal logic, and input boundary logic;   prohibiting said test pattern scan information from application to said input boundary logic when a self test signal is in a first state, said prohibition providing no transmission delay between a receiver and said input boundary logic;   said test pattern scan information being applied to said input boundary logic through a tristate pass gate when self test signal is in a second state;   sampling scan information from said internal logic and said input boundary logic, said sampled scan information being stored in a multiple input shift register; and   comparing said sampled test data with signature test data results to determine said self testable logic circuit functional performance.