Selective operation of processing elements in a single instruction multiple data stream (SIMD) computer system

Abstract

A plurality of processing elements independently operate in parallel on separate streams of data but in response to common instructions. In order to selectively and individually enable each processing element, a control register stage is provided for each. Each register may be controlled, as between its enabling and disabling states with respect to execution of a common instruction, by the results of a test performed by its associated processor in response to a prior instruction and by the complement of the test results. The system is especially adapted to support flow of control operators, such as IF/THEN constructs, IF/THEN/ELSE constructs and WHILE/DO loop constructs.

It is claimed: 
     
       1. A processing system for providing parallel processing in a conditional branching environment without prescheduling and pre-formatting of instructions, said processing system comprising: a plurality of processing means, said processing means coupled in parallel to a first bus;   a plurality of data lines, each of said plurality of said processing means coupled to corresponding one of said plurality of data lines;   a plurality of control registers, each of said control registers coupled to corresponding one of said plurality of processing means, said control registers for enabling and disabling said processing means, said control registers coupled in parallel to a second bus;   programming means coupled to said first and second bus, said programming means for providing instructions to said processing means on said first bus for testing data produced by said processing means and for providing enable signals to said control registers on said second bus;   a plurality of output buses, each of said output buses coupled to corresponding one of said plurality of processing means and to said programming means;   said programming means providing an instruction sequence of at least first and second instructions on said first bus to each of said processing means in time sequence, said first instruction executed by each of said processing means producing data on said plurality of output buses, said data tested by said programming means against a common condition, said programming means outputting on said second bus an enable signal to certain of said plurality of control registers, said certain of said control registers providing said enable signal to said processing means such that said second instruction is executed only in those processing means where said test of said data has provided a certain pre-defined result, said programming means then outputting a signal which enables the disabled processing means and disables the previously enabled processing means, and at least a third instruction nested between said first and second instructions is executed in those now enabled processing means where said test of said data has not provided said certain pre-defined result;   storage means coupled to said control registers for temporarily storing the contents of said control registers when said at least third instruction is executed between said first and second instructions during conditional branching of said instruction sequence, said storage means retaining the results of the test of said first instruction and providing said results to said control registers for execution of said second instruction when said conditional branching is completed.   
     
     
       2. The system of claim 9 wherein said first instruction includes an IF instruction and said second instruction includes an ELSE instruction. 
     
     
       3. A processing means for providing parallel processing in a conditional branching environment without prescheduling and pre-formatting of instructions, said processing means comprising: first, second, third and fourth processors, said processors coupled to red, green, blue and alpha (RGBA) data channels respectively, said data channels providing data to said processors said processors having first, second, third and fourth outputs, respectively, said outputs of said processors coupled to a first bus;   first, second, third and fourth control registers coupled to said first through fourth processors respectively and to a second bus;   program sequencing means coupled to said first bus and said second bus, said sequencing means providing at least first and second instructions in time sequence to said processors, causing each of said processors to execute said first instruction and produce a first output signal;   said first output signal tested by said sequencing means against a common condition, said sequencing means outputting an enable signal on said second bus to certain of said control registers, said certain control registers providing said enable signals to said processors such that said second instruction is executed only in those processors where the test of said first output signal has provided a certain pre-defined result, said sequencing means then outputting a signal which enables the disabled processors and disables the previously enabled processors, and at least a third instruction nested between said first and second instructions is executed in those now enabled processing means where said test of said data has not provided said certain pre-defined result;   said first instruction including an IF instruction, said second instruction including an ELSE instruction;   storage means coupled to said registers for temporarily storing the contents of said registers, wherein said at least third instruction is executed between said first and second instructions while said storage means retains the results of the test of said first instruction and provides said results to said control registers for execution of said second instruction.