Video codec including pipelined processing elements

Abstract

A videophone system for providing videophone service within narrow band digital network, based on pipelined processing elements, includes source codec means coupled to the image bus, including numerous processing elements of which processing element has DSP (Digital Signal Processor) module, local memory module coupled to the DSP module, FIFO (First Input First Output) memory module coupled to the DSP module and the local memory module, and image bus interface module coupled to the DSP module and the local memory module and the image bus, wherein communications between the processor elements is performed via the pipeline and common memory means coupled to the VME bus and the image bus, for storing message data for synchronization and communication between the processing elements.

What is claimed is: 
     
       1. In videophone system for providing videophone service within narrow band digital network, including transmission codec means for connecting to the narrow band digital network, VME (Versa Module Europe) bus and image bus coupled to the transmission codec means, camera, TV monitor, A/D (Analog to Digital) and D/A converter coupled to the camera and the TV monitor, and frame memory means coupled to the A/D and D/A converter and the image bus, a videophone system further comprising; source codec means coupled to the image bus, including a plurality of processing elements of which processing element has DSP (Digital Signal Processor) module, local memory module coupled to the DSP module, FIFO (First Input First Output) memory module coupled to the DSP module and the local memory module, and image bus interface module coupled to the DSP module, the local memory module and the image bus, wherein communications between the processing elements are performed via pipeline, and   common memory means coupled to the VME bus and the image bus, for storing message data for synchronization and communication between the processing elements.   
     
     
       2. A videophone system according to claim 1, the FIFO memory module including a flag circuit which is comprised of an address decoder coupled to the DSP module, first and second D flip-flops coupled to the other processing element, and a selection switch coupled to the first and second D flip-flops and the DSP module and the address decoder in order to select one of the two D flip-flop outputs and to send to the DSP module.