High speed asynchronous data interface

Abstract

A digital data interface for high speed asynchronous data transfer is described. The design is nominally intended for integration onto the component chips in communications systems. The system is described with respect to its realization in CMOS IC technology. The techniques involved, however, may easily be applied to other technologies. The interface employs Manchester Bi-Phase Mark encoding of the clock and data to allow extraction of the clock and data signals at the receiver. Furthermore, use of this Manchester code allows code violations to be easily employed as frame markers for synchronization means. The essence of the clock extraction and data detection circuit is the use of calibrated delay line elements to suppress data transitions within the coded input signal, thus allowing the clock transitions to be detected from which the clock is then generated.

We claim: 
     
       1. A high speed asynchronous data interface comprising at least one interface transmitter and at least one interface receiver, and a transmission line interconnecting the transmitter and receiver, by way of which data is transmitted from the transmitter to the receiver, wherein each receiver includes a data decoder and data clock extraction circuit which are connected to a data alignment circuit arranged to generate output data, characterized in that the data clock extraction circuit comprises a delay line, a latch and a transient detector, the latch receiving from the transient detector a set pulse at an input for each transient state of the data, and causing an output of the latch to adopt a low logic level, the output of the latch is coupled to the delay line which propagates the low level and generates a reset pulse which resets the latch and restores a high logic level at the output of the latch, wherein, any data dependent transient pulse generated while the latch is reset is overidden at this time and the clock is extracted from the output of the latch. 
     
     
       2. A high speed asynchronous data interface as claimed in claim 1, wherein the delay line is controllable and comprises two stages, and a further third stage of the delay line is provided for sampling the state of the latch during a subsequent bit cycle, and wherein there is provided a second latch to which said third stage is connected, which second latch receives the output from the first latch, and if the output from the first latch has not been triggered by a succeeding clock transient and is still high, a code violation is indicated by the output of the second latch. 
     
     
       3. A high speed asynchronous data interface as claimed in claim 2, wherein the transient detector comprises two negative edge-triggered monostables each comprising an inverter and an OR-gate. 
     
     
       4. A high speed asynchronous data interface as claimed in claim 3, wherein the clock extraction circuit is connected to a phase-locked loop circuit which generates a control signal for the delay line. 
     
     
       5. A high speed asynchronous data interface as claimed in claim 4, wherein the phase-locked loop circuit includes a voltage controlled oscillator which generates the control signal in synchronism with the clock.