Circuit for preservation of sign information in operations for comparison of the absolute value of operands

Abstract

A circuit for preserving sign information in a computer system. The computer system is capable of comparing and operating on the absolute value of two operands utilizing a pipelined architecture. Sign information is preserved through the use of a first plurality of stages corresponding to stages of the pipeline for storing sign information of a first operand and a second plurality of stages corresponding to stages of the pipeline for storing sign information of a second operand. Sign information is piped through the first and second plurality of stages under common control with the control for the pipeline. Upon completion of the comparison operation, the sign information for the operands is available. Further, the sign information for the first and second operands are coupled as inputs to a multiplexor. The multiplexor is controlled to select either the sign information of the first operand or the sign information of the second operand for storage as the sign of the result depending on the result of the comparison operation.

What is claimed is: 
     
       1. A computer having: (1) processing means for processing information;   (2) storage means for storing information;   (3) input/output means for communicating information with at least one peripheral device; and   (4) communication means for communicating information between said processing means, said storage means and said input/output means; wherein said processing means includes:   (5) a first input coupled to said communicating means for receiving a first operand;   (6) a second input coupled to said communication means for receiving a second operand;   (7) comparison means coupled to said first input and said second input, said comparison means for comparing the absolute value of said first operand and said second operand, said comparison means having N stages;   (8) first sign preservation means coupled to said comparison means, said first sign preservation means for preserving sign information for said first operand, said first sign preservation means having a first N storage means corresponding to said N stages; and   (9) second sign preservation means coupled to said comparison means, said second sign preservation means for preserving sign information for said second operand, said second sign preservation means having a second N storage means corresponding to said N stages.   
     
     
       2. The computer as recited by claim 1 wherein said comparison means, said first sign preservation means and said second sign preservation means operate under common control. 
     
     
       3. The computer as recited by claim 2 wherein further comprising multiplexor means coupled to receive a first sign information from said first sign preservation means and a second sign information from said second sign preservation means, said multiplexor means controlled to present either said first sign information or said second sign information depending on the result of a comparison operation executed by said comparison means. 
     
     
       4. The computer as recited by claim 3 wherein N is equal to 5. 
     
     
       5. In a pipelined computer having: (1) a first stage for receiving a first and second operand into a first and a second input from a memory;   (2) a second stage for loading a multiplication means, said multiplication means coupled to said first and second input;   (3) a third stage for executing a multiplication instruction on said first and second operand;   (4) a fourth stage for loading and executing an addition instruction by an addition means, said addition means coupled to an output of said multiplication means and to an output of said addition means;   (5) a fifth stage for unloading said addition means; the improvement comprising:   (6) first pipeline for piping sign information of said first operand, said first pipeline having a first stages 1-5 corresponding to said first through fifth stages of said pipelined computer;   (7) second pipeline for piping sign information of said second operand, said second pipeline having a second stages 1-5 corresponding to said first through fifth stages of said pipelined computer.   
     
     
       6. The computer as recited by claim 5 wherein said first stage 1 said first pipeline and said first stage of said computer operate under common control; said first stage 2 of said first pipeline and said second stage of said computer operate under common control; said first stage 3 of said first pipeline and said third stage of said computer operate under common control; said first stage 4 of said first pipeline and said fourth stage of said computer operate under common control; and said first stage 5 of said first pipeline and said fifth stage of said computer operate under common control. 
     
     
       7. The computer as recited by claim 6 further comprises means for selecting between a first bit in a first word of said first operand and a second bit in a second word of said first operand for piping in said first pipeline. 
     
     
       8. The computer as recited by claim 7 further comprising means for selecting sign information from either said first pipeline or said second pipeline, said means for selecting sign information coupled to receive a first sign bit from said first pipeline and a second sign bit from said second pipeline.