Ecl output buffer circuit with improved compensation

Abstract

An ECL output buffer circuit for generating a stable predetermined output voltage over power supply, temperature and process variations and having a high speed of operation with low power consumption includes a differential pair formed of first and second input transistors (Q102, Q103), an emitter follower transistor (Q101), a first current source (112), and a second current source (114). The first current source is coupled to the base of the emitter follower transistor for generating a compensating current. The second current source is coupled to the emitters of the first and second input transistors for generating a gate current. <IMAGE>

What is claimed is: 
     
       1. An ECL output buffer circuit for generating a stable predetermined output voltage swing over power supply, temperature and process variations which has a high speed of operation with low power consumption comprising: a differential pair formed of first and second input transistors (Q102, Q103) having their emitters connected together, said first input transistor (Q102) having its base connected to receive a true input logic signal and its collector connected to a first supply potential (GCML) via a first load resistor (R102), said second input transistor (Q103) having its base connected to receive a complementary input logic signal and its collector connected to the first supply potential (GCML) via a second load resistor (R101);   an emitter follower transistor (Q101) having its collector connected to a ground potential (GECL), its base connected to the collector of said second input transistor (Q103), its emitter connected to an output terminal for generating the stable output voltage swinging between a high logic level and a low logic level;   first current source means (112) coupled between the base of said emitter follower transistor (Q101) and a second supply potential (VEE) for generating a compensating current;   second current source means (114) coupled between the common emitters of said first and second input transistors (Q102, Q103) and the second supply potential (VEE) for generating a gate current;   said first current source means (112) being formed of a first current source transistor (Q105) and a first emitter resistor (R103), said first current source transistor (Q105) having its collector connected to the base of said emitter follower transistor (Q101), its base coupled to receive a first stable reference voltage (V CSH ), and its emitter connected to one end of the first emitter resistor (R103), the other end of the first emitter resistor (R103) being connected to the second supply potential (VEE); and   said first reference voltage being generated by a first bandgap reference voltage generator (113).   
     
     
       2. An ECL output buffer circuit as claimed in claim 1, wherein said second current source means (114) is formed of a second current source transistor (Q106) and a second emitter transistor (R104), said second current source transistor (Q104) having its collector connected to the common emitters of said first and second input transistors (Q102, Q103), its base connected to receive a second stable reference voltage (V CSL ), and its emitter connected to one end of the second emitter resistor (R104), the other end of the second emitter resistor (R104) being connected to the second supply potential (VEE). 
     
     
       3. An ECL output buffer circuit as claimed in claim 2, wherein said second stable reference voltage is generated by a second bandgap reference voltage generator (115). 
     
     
       4. An ECL output buffer circuit as claimed in claim 1, wherein said second current source means (114) is switched off for generating the high output level and is switched on for generating the low output level. 
     
     
       5. An ECL output buffer circuit as claimed in claim 1, further comprising level shifting means (116) interconnecting said first reference voltage and the base of said first current source transistor (Q105). 
     
     
       6. An ECL output buffer circuit as claimed in claim 5, wherein said level-shifting means (116) is formed of a third transistor (Q106) and an emitter resistor (R105), said third transistor having its collector coupled to the first supply potential (GCML) via a load resistor (R106), its base connected to receive the first stable reference voltage (V CSH ) and its emitter connected to one end of the emitter resistor (R105) and to the base of the first current source transistor (Q105), the other end of the emitter resistor (R105) being connected to the second supply potential (VEE). 
     
     
       7. An ECL output buffer circuit as claimed in claim 6, wherein said first power supply potential (GCML) is at typically zero volts and wherein said second supply potential is at typically -5.2 volts. 
     
     
       8. An ECL output buffer circuit for generating a stable predetermined output voltage swing over power supply, temperature and process variations which has a high speed of operation with low power consumption comprising: a differential pair formed of first and second input transistors (Q102, Q103) having their emitters connected together, said first input transistor (Q102) having its base connected to receive a true input logic signal and its collector connected to a first supply potential (GCML) via a first load resistor (R102), said second input transistor (Q103) having its base connected to receive a complementary input logic signal and its collector connected to the first supply potential (GCML) via a second load resistor (R101);   an emitter follower transistor (Q101) having its collector connected to a ground potential (GECL), its base connected to the collector of said second input transistor (Q103), its emitter connected to an output terminal for generating the stable output voltage swinging between a high logic level and a low logic level;   first compensating means (112) coupled between the base of said emitter follower transistor (Q101) and a second supply potential (VEE) for generating a compensating current;   second compensating means (114) coupled between the common emitters of said first and second input transistors (Q102, Q103) and the second supply potential (VEE) for generating a gate current;   said first compensating means (112) being formed of a current source transistor (Q105) and an emitter resistor (R103), said current source transistor (Q105) having its collector connected to the base of said emitter follower transistor (Q101), its base coupled to receive a first stable reference voltage (V CSH ), and its emitter connected to one end of the emitter resistor (R103), the other end of the emitter resistor (R103) being connected to the second supply potential (VEE); and   said first reference voltage being generated by a first bandgap reference voltage generator (113).   
     
     
       9. An ECL output buffer circuit as claimed in claim 8, wherein said second compensating means (114) is formed of a current source transistor (Q106) and an emitter transistor (R104), said current source transistor (Q104) having its collector connected to the common emitters of said first and second input transistors (Q102, Q103), its base connected to receive a second stable reference voltage (V CSL ), and its emitter connected to one end of the emitter resistor (R104), the other end of the emitter resistor (R104) being connected to the second supply potential (VEE). 
     
     
       10. An ECL output buffer circuit as claimed in claim 9, wherein said second stable reference voltage is generated by a second bandgap reference voltage generator (115). 
     
     
       11. An ECL output buffer circuit as claimed in claim 8, wherein said second compensating means (114) is switched off for generating the high output level and is switched on for generating the low output level. 
     
     
       12. An ECL output buffer circuit as claimed in claim 8, further comprising level shifting means (116) interconnecting said first reference voltage and the base of said first current source transistor (Q105). 
     
     
       13. An ECL output buffer circuit as claimed in claim 12, wherein said level-shifting means (116) is formed of a third transistor (Q106) and an emitter resistor (R105), said third transistor having its collector coupled to the first supply potential (GCML) via a load resistor (R106), its base connected to receive the first stable reference voltage (V CSH ) and its emitter connected to one end of the emitter resistor (R105) and to the base of the first current source transistor (Q105), the other end of the emitter resistor (R105) being connected to the second supply potential (VEE). 
     
     
       14. An ECL output buffer circuit as claimed in claim 8, wherein said first power supply potential (GCML) is at typically zero volts and wherein said second supply potential is at typically -5.2 volts. 
     
     
       15. An ECL output buffer circuit comprising: output transistor means (Q101) for generating a stable predetermined output voltage swinging between a high logic level and a low logic level;   first differential means (Q102, Q103) responsive to input logic signals for switching off and on said output transistor means to provide the high and low logic levels;   first compensating means (112) coupled to said output transistor means for generating a compensating current;   second differential means (Q107, Q108) responsive to said input logic signals for selectively coupling said first compensating means to said output transistor means;   second compensating means (114) coupled to said first differential means for generating a gate current;   first bandgap generator means (113) coupled to said first compensating means (112); and   second bandgap generator means (115) coupled to said second compensating means (114).