Power efficient sustain drivers and address drivers for plasma panel

Abstract

An improved address driver circuit for plasma panels, particularly useful with an independent sustain and address plasma panel. Address pulse generators for one panel address axis are coupled to MOSFET driver devices and provide pulses of a first polarity; and address pulse generators for the other panel address axis are coupled to similar MOSFET driver devices and provide double pulses of a second polarity. With N-channel open-drain MOSFET drivers on both panel address axes, they only need to be designed to pull low. An improved power efficient sustain driver for plasma panels including an inductor through which the panel capacitance is charged and discharged, and switch means switched when the inductor current is zero, which permits recovery of the energy otherwise lost in driving the panel capacitance. An independent sustain and address plasma panel with such energy efficient address drivers and sustain drivers. The energy efficient sustain driver can be used with plasma display panels, electroluminescent panels and with liquid crystal panels having inherent panel capacitance. An independent sustain and address panel with N-channel MOSFET drivers on one address axis and P-channel MOSFET drivers on the other address axis, with an address pulse generator providing pulses of a first polarity to the N-channel MOSFETs, and another address pulse generator providing pulses of a second polarity to the P-channel MOSFETS.

We claim: 
     
       1. Addressing apparatus for addressing cells defined by the intersection of respective address electrodes in respective arrays of X and Y dimension address electrodes in an ac plasma panel, said addressing apparatus comprising: means for applying a high level pulse of one polarity to a plurality of address electrodes of one dimension array;   means for selective discharging of non-selected address electrodes of said plurality and maintaining the high level of one polarity at selected address electrodes of said plurality in accordance with desired information to be entered into the plasma panel; and   means for applying a high level pulse of opposite polarity to respective address electrode of the other dimension array after said selective discharging of non-selected address electrodes for discharging cells at said selected address electrodes and entering the desired information into the plasma panel.   
     
     
       2. Addressing apparatus according to claim 1, including means for applying a second high level pulse of said one polarity to said plurality of address electrodes of said one dimension array after the end of said high level pulse of opposite polarity for enabling the controllable discharging of said selected address electrodes from said high level to said low level of said one polarity. 
     
     
       3. Addressing apparatus for addressing cells defined by the intersection of respective address electrodes in respective arrays of X and Y dimension address electrodes in an ac plasma panel, said addressing apparatus comprising: means for charging a plurality of address electrodes of one dimension array to a high level of one polarity;   means for selective discharging of non-selected charged address electrodes of said plurality and maintaining the high level of one polarity at selected charged address electrodes in accordance with desired information to be entered into the plasma panel; and   means for applying a high level of opposite polarity charge to a respective address electrode of the other dimension array after said selective discharging of non-selected charged address electrodes for discharging cells at said selected charged address electrodes and entering the desired information into the plasma panel.   
     
     
       4. Addressing apparatus according to claim 3, wherein said means for charging said plurality of address electrode of one dimension array includes means for applying a high level pulse of said one polarity to said plurality of address electrodes. 
     
     
       5. Addressing apparatus according to claim 3, including means for applying a high level pulse of said one polarity to said plurality of address electrodes of one dimension array after entering said desired information into the plasma panel for enabling the controllable discharging of said selected charged address electrodes from said high level to said low level of said one polarity. 
     
     
       6. Addressing apparatus according to claim 5, wherein said means for charging said plurality of address electrodes of one dimension array includes means for applying a high level pulse of said one polarity to said plurality of address electrodes. 
     
     
       7. A method of addressing address cells defined by the intersection of respective address electrodes in respective arrays of X and Y dimension address electrodes in an ac plasma panel, said method of addressing comprising the steps of: charging a plurality of address electrodes of one dimension array to a high level of one polarity;   selective discharging of non-selected charged address electrodes of said plurality without discharging selected charged address electrodes of said plurality in accordance with desired information to be entered into the plasma panel; and   applying a high level of opposite polarity charge to a respective address electrode of the other dimension array for discharging address cells associated with the selected charged address electrodes of said plurality and entering the desired information into the plasma panel.   
     
     
       8. The method of claim 7, wherein said charging includes applying a high level pulse of said one polarity to said plurality of address electrodes of one dimension array. 
     
     
       9. The method of claim 7, including the further step of applying a high level pulse of said one polarity to said plurality of address electrodes of one dimension array after entering said desired information into the plasma panel for enabling the controllable discharging of said selected charged address electrodes. 
     
     
       10. The method of claim 9, wherein said charging includes applying a first high level pulse of said one polarity to said plurality of address electrodes of one dimension array. 
     
     
       11. Addressing apparatus for addressing pixels defined by the intersection of respective address electrodes in respective arrays of X and Y dimension address electrodes in a display panel, said addressing apparatus comprising: means for applying a high level pulse of one polarity to address electrodes of one dimension array;   means for selective discharging of non-selected address electrodes without discharging selected address electrodes in accordance with desired information to be entered into the display panel; and   means for applying a high level pulse of opposite polarity to a respective address electrode of the other dimension array after said selective discharging for entering the desired information into the display panel.   
     
     
       12. Address apparatus according to claim 11, including means for applying a second high level pulse of said one polarity to said address electrodes of said one dimension array after the end of said high level pulse of opposite polarity for enabling the controllable discharging of said selected address electrodes. 
     
     
       13. Addressing apparatus for addressing pixels defined by the intersection of respective address electrodes in respective arrays of X and Y dimension address electrodes in a display panel, said addressing apparatus comprising: means for charging address electrodes of one dimension array to a high level of one polarity;   means for selective discharging of non-selected charged address electrodes without discharging selected charged address electrodes to maintain the high level of one polarity at said selected charged address electrodes in accordance with desired information to be entered into the display panel; and   means for applying a high level of opposite polarity charge to a respective address electrode of the other dimension array after said selective discharging of non-selected charged address electrodes for entering the desired information into the display panel.   
     
     
       14. Address apparatus according to claim 13, including means for applying a high pulse of said one polarity to said address electrodes of one dimension array after entering said desired information into the display panel for enabling the controllable discharging of said selected charged address electrodes from said high level to a low level of said one polarity. 
     
     
       15. A method of addressing address cells defined by the intersection of respective address electrodes in respective arrays of X and Y dimension address electrodes in a display panel, said method of addressing comprising the steps of: charging address electrodes of one dimension array to a high level of one polarity;   selective discharging non-selected but not selected charged address electrodes in accordance with desired information to be entered into the display panel; and   applying a high level of opposite polarity charge to a respective address electrode of the other dimension array after said selective discharging for entering the desired information into the display panel.   
     
     
       16. The method of claim 15, including the further step of applying a high level pulse of said one polarity to said address electrode of one dimension array after entering said desired information into the display panel for enabling the controllable discharging of said selected charged address electrodes. 
     
     
       17. A display panel comprising: an array of X dimension address electrodes;   an intersecting array of Y dimension address electrodes, where intersections between respective X and Y address electrodes define respective display pixels;   address means for applying an addressing signal during an addressing cycle to selected X and Y address electrodes to activate at least one display pixel;   said address means including, means for charging more than one address electrode of said X or Y dimension array to a high level of one polarity;   means for selective discharging non-selected but not selected charged address electrodes in accordance with desired information to be entered into the display panel; and   means for applying a high level pulse of opposite polarity to a respective address electrode of the other said X or Y dimension array after said selective discharging for entering the desired information into the display panel.   
     
     
       18. A display panel according to claim 17, including means for enabling controllable discharging of said address electrode from said high level of said one polarity after entering said desired information into the display panel. 
     
     
       19. An ac plasma panel comprising: an array of X dimension electrodes;   an intersecting array of Y dimension electrodes with the intersections between respective X and Y electrodes defining a gas discharge cell;   address means for applying a signal to selected X and Y electrodes to discharge at least one gas discharge cell;   said address means including, means for charging more than one address electrode of said X or Y dimension array to a high level of one polarity;   means for selective discharging nonselected but not selected charged address electrodes to maintain the high level of one polarity at said selected charged address electrodes in accordance with desired information to be entered into the plasma panel; and   means for applying a high level pulse of opposite polarity to a respective address electrode of the other said X or Y dimension array after said selective discharging for discharging said one gas discharge cell and entering the desired information into the plasma panel.   
     
     
       20. An ac plasma panel according to claim 19, including means for enabling controllable discharging of said selected charged address electrodes from said high level to a low level of said one polarity after entering said desired information into the plasma panel. 
     
     
       21. In display panels having panel electrodes and corresponding panel capacitance, an energy efficient method of driving said display panels through an inductor coupled to the panel electrodes comprising the steps of: charging the panel capacitance through said inductor, initially while storing energy in said inductor until the magnitude of the inductor current reaches a maximum, and secondly while removing the stored energy from said inductor until the inductor current reaches zero; and   discharging the panel capacitance through said inductor, initially while storing energy in said inductor until the magnitude of the inductor current reaches a maximum, and secondly while removing the stored energy from said inductor until the inductor current reaches zero.   
     
     
       22. The method of claim 21, wherein charging of the panel capacitance includes applying a forcing voltage which is about one-half the magnitude of the voltage level the panel capacitance reaches after charging. 
     
     
       23. The method of claim 22, wherein discharging of the panel capacitance includes applying a forcing voltage which is about one-half the magnitude of the voltage level the panel capacitance reaches after charging. 
     
     
       24. The method of claim 21, including the step of after discharging the panel capacitance, maintaining the panel capacitance in a discharging state prior to again charging the panel capacitance. 
     
     
       25. The method of claim 21, including the steps of after charging the panel capacitance, maintaining the panel capacitance in a charged state prior to discharge, and after discharge, maintaining the panel capacitance in a discharged state prior to again charging the panel capacitance. 
     
     
       26. The method of claim 25, wherein the step of maintaining the panel capacitance in a charged state includes clamping the voltage level of the panel capacitance upon the inductor current reaching zero, and wherein the step of maintaining the panel capacitance in a discharged state prior to again charging includes clamping the voltage level of the panel capacitance upon the inductor current reaching zero. 
     
     
       27. A display panel having panel electrodes and panel capacitance, an inductor coupled to the panel electrodes, and a driver circuit coupled to the inductor for operating the display panel through the inductor, the driver circuit including, means for charging the panel capacitance through said inductor, initially while storing energy in said inductor until the magnitude of the inductor current reaches a maximum, and secondly while removing the stored energy from said inductor until the inductor current reaches zero; and   means for discharging the panel capacitance through said inductor, initially while storing energy in said inductor until the magnitude of the inductor current reaches a maximum, and secondly while removing the stored energy from said inductor until the inductor current reaches zero.   
     
     
       28. A display panel according to claim 27, wherein said means for charging the panel capacitance includes means for applying a forcing voltage which is about one-half the magnitude of the voltage level the panel capacitance reaches after charging. 
     
     
       29. A display panel according to claim 28, wherein said means for discharging the panel capacitance includes means for applying a forcing voltage which is about one-half the magnitude of the voltage level the panel capacitance reaches after charging. 
     
     
       30. A display panel according to claim 27, including means for maintaining the panel capacitance in a discharged state upon the inductor current reaching zero and prior to again charging the panel capacitance. 
     
     
       31. A display panel according to claim 27, including means for maintaining the panel capacitance in a charged state after charging the panel capacitance and prior to discharge, and means for maintaining the panel capacitance in a discharged state after discharge and prior to again charging the panel capacitance. 
     
     
       32. A display panel according to claim 31, wherein said means for maintaining the panel capacitance in a charged state includes means for charging the voltage level of the panel capacitance upon the inductor current reaching zero during charging of the panel capacitance, and wherein said means for maintaining the panel capacitance in a discharged state includes means for clamping the voltage level of the panel capacitance upon the inductor current reaching zero during discharging of the panel capacitance. 
     
     
       33. A display panel having panel electrodes and panel capacitance, and an energy recovery sustain circuit coupled to the panel electrodes for driving said display panel, said energy recovery sustain circuit including; an inductor coupled to said panel electrodes for charging and discharging the panel capacitance;   means for charging the panel capacitance through said inductor, initially while storing energy in said inductor until the magnitude of the inductor current reaches a maximum, and secondly while removing the stored energy from said inductor until the inductor current reaches zero;   first means for clamping the voltage level of said panel capacitance upon the inductor current reaching zero during charging of the panel capacitance;   means for discharging the panel capacitance through said inductor, initially while storing energy in said inductor until the magnitude of the inductor current reaches a maximum, and secondly while removing the stored energy from said inductor until the inductor current reaches zero; and   second means for clamping the voltage level of the panel capacitance upon the inductor current reaching zero during discharging of the panel capacitance.   
     
     
       34. A display panel according to claim 33, wherein said first and second means for clamping includes means responsive to the inductor current reaching zero to provide said clamping independent of variations in the values of said inductor or said panel capacitance. 
     
     
       35. An energy efficient driver circuit for driving display panels having panel electrodes and panel capacitance, said driver circuit comprising: an inductor coupled to said panel electrodes for charging and discharging the panel capacitance;   means for charging the panel capacitance through said inductor, initially while storing energy in said inductor until the magnitude of the inductor current reaches a maximum, and secondly while removing the stored energy from said inductor until the inductor current reaches zero; and   means for discharging the panel capacitance through said inductor, initially while storing energy in said inductor until the magnitude of the inductor current reaches a maximum, and secondly while removing the stored energy from said inductor until the inductor current reaches zero.   
     
     
       36. An energy efficient sustainer circuit for driving display panels having panel electrodes and panel capacitance, said sustainer circuit comprising an inductor coupled to said panel electrodes for charging and discharging the panel capacitance;   means for charging the panel capacitance through said inductor, initially while storing energy in said inductor until the magnitude of the inductor current reaches a maximum, and secondly while removing the stored energy from said inductor until the inductor current reaches zero; and   first means for clamping the voltage level of the panel capacitance upon the inductor current reaching zero during charging of the panel capacitance;   means for discharging the panel capacitance through said inductor, initially while storing energy in said inductor until the magnitude of the inductor current reaches a maximum, and secondly while removing the stored energy from said inductor until the inductor current reaches zero; and   second means for clamping the voltage level of the panel capacitance upon the inductor current reaching zero during discharging of the panel capacitance.   
     
     
       37. An energy efficient sustainer circuit according to claim 36, wherein said first and second means for clamping includes means responsive to the inductor current reaching zero to provide said clamping independent of variations in the values of said inductor or said panel capacitance. 
     
     
       38. An energy efficient driver circuit for driving display panels having panel electrodes and panel capacitance, said driver circuit comprising: an inductor coupled to said panel electrodes for charging and discharging said panel capacitance respectively to and from a desired voltage level magnitude;   first switch means coupled to said inductor to enable said panel capacitance to charge through said inductor from a first voltage level (a) initially to an intermediate voltage level magnitude which is about one-half the desired voltage level magnitude, while storing energy in said inductor, and (b) then to said desired voltage level magnitude, while removing said stored energy from said inductor; and   second switch means coupled to said inductor to enable said panel capacitance to discharge through said inductor from said desired voltage level magnitude (a) initially to an intermediate voltage level magnitude which is about one-half the desired voltage level magnitude, while storing energy in said inductor, and (b) then to said first voltage level magnitude, while removing said stored energy from said inductor.   
     
     
       39. An energy efficient driver according to claim 38, including third switch means coupled to said inductor for clamping the panel capacitance voltage level to maintain a panel capacitance discharged state until the panel capacitance is again charged. 
     
     
       40. An energy efficient driver according to claim 38, including third switch means coupled to said inductor clamping the panel capacitance voltage to said desired voltage level magnitude after charging of said panel capacitance, and fourth switch means coupled to said inductor for clamping the panel capacitance voltage to said first voltage level magnitude after discharging of said panel capacitance. 
     
     
       41. An energy efficient driver according to claim 40, wherein said third switch means and said fourth switch means each respectively includes means responsive to the end of the removal of said stored energy from said inductor to provide said respective clamping independent of variations in the value of said inductor or said panel capacitance.