Apparatus for page mode programming of an EEPROM cell array with false loading protection

Abstract

An apparatus for page mode programming of an EEPROM cell array with false loading protection is disclosed. The system includes a flip-flop operatively connected to a bit line for storing information to be loaded into an EEPROM memory cell, and false loading protection circuitry operatively connected to the bit line for preventing the false loading of an erroneous signal into the flip-flop and/or an EEPROM cell.

What is claimed is: 
     
       1. An apparatus for preventing false loading of information into a temporary storage device operative during page mode programming of a memory cell array, wherein said temporary storage device is operatively connected to a bit line connected to a plurality of memory cells, including: a first transistor and a second transistor, said first transistor having a drain connected to said bit line and a source connected to a drain of said second transistor, a source of said second transistor connected to a source of voltage to which said bit line is to be discharged, said first transistor having a gate connected to a signal which renders said first transistor conductive during a page mode programming loading sequence for said memory array and said second transistor having a gate connected to a signal which renders said second transistor conductive when no memory cell associated with said bit line has been selected for programming.