Wafer alignment mark utilizing parallel grooves and process

Abstract

A wafer alignment mark consists of patterns, such as a chevron and two stripes, formed in the surface of a semiconductor wafer. Each pattern is defined by a pair of parallel grooves, separation between all pairs of grooves being the same. Each groove provides one sharp edge which can be reliably detected by an automatic alignment system. A wafer fabrication process uses peripheral etching to form grooves in a wafer substrate around the periphery of windows opened for dopant diffusion and alignment mark formation, and forms Si 3 N 4 tapers in the grooves. Although ultimately removed, the grooves create a pattern with nearly vertical sidewalls in the substrate which, when transferred to an epitaxial layer, forms wafer alignment marks with sharp edges.

What is claimed is: 
     
       1. A wafer alignment mark for aligning a semiconductor wafer with a mask, comprising: a first alignment pattern comprising a first pair of parallel patterns, mutually separated by a constant distance A, intersecting at an angle a second pair of parallel alignment patterns, also mutually separated by the constant distance A;   a second alignment pattern comprising a third pair of parallel, straight patterns, parallel to said first pair of parallel patterns, and located on another side of said first pattern; and   a third alignment pattern comprising a fourth pair of parallel, straight patterns, parallel to said second pair of parallel patterns, and located on another side of said first pattern,   said first, second, and third alignment patterns being detectable on a single side of the wafer.   
     
     
       2. The wafer alignment mark of claim 1 wherein said third and fourth parallel patterns are separated by said constant distance A. 
     
     
       3. The alignment mark of claim 1 wherein said distance A is between ten micrometers and twenty-five micrometers. 
     
     
       4. The alignment mark of claim 1 wherein said second and third alignment patterns are disposed at a distance of seventy-five micrometers to one-hundred fifty micrometers from said first alignment pattern. 
     
     
       5. The alignment mark of claim 1 wherein each of said alignment patterns comprise grooves. 
     
     
       6. The alignment mark of claim 1 wherein said angle is a right angle. 
     
     
       7. The alignment mark of claim 1 wherein the mask includes alignment patterns mutually separated by a distance A and parallel to at least one alignment pattern on said wafer. 
     
     
       8. A wafer alignment mark for aligning a semiconductor wafer with a mask, comprising: a first pair of parallel grooves mutually separated by a constant distance A, formed on a surface of said wafer, each groove comprising two straight sections joined at a right angle;   a second pair of parallel, straight grooves, mutually separated by the same distance A, formed on said surface and parallel to said first pair of grooves on one side of said right angle; and   a third pair of parallel, straight grooves, mutually separated by the same distance A, formed on said surface and parallel to said first pair of grooves on another side of said right angle.   
     
     
       9. The alignment mark of claim 8, wherein said grooves are between two and three micrometers wide. 
     
     
       10. The alignment mark of claim 9, wherein said distance A is between ten micrometers and twenty-five micrometers. 
     
     
       11. The alignment mark of claim 10, wherein said second pair of grooves and said third pair of grooves are disposed at a distance of seventy-five micrometers to one-hundred fifty micrometers from said first pair of grooves. 
     
     
       12. The alignment mark of claim 8 wherein the mask includes mask alignment patterns parallel to at least one pair of parallel grooves on said wafer.