Solid-state imaging device

Abstract

A solid-state imaging device constructed according to the TSL system having a plurality of photodiodes arrayed in matrix form so as to serve as a group of pixels, a vertical selection gate line extending from a vertical scanning circuit, a horizontal selection gate line extending from a horizontal scanning circuit, and a signal read line. A projection made of an impurity layer identical to that of the photodiodes is formed at an end of each of the photodiodes. A first switching transistor is formed by interconnecting the vertical selection gate line made of a polysilicon layer so as to cross over an upper surface of each of the projections. A second switching transistor is formed by laminating a gate portion made of a polysilicon layer on the other upper surface of each of the projections. Horizontal selection gate lines are formed by connecting between the vertically arrayed gate portions and an interconnection made of a conductor layer such as an aluminum layer insulatively laminated above the polysilicon layer. Signal read lines are formed by a conductive layer fabricated by a process identical to that of the conductive layer, and each signal read line is interconnected so that the upper surface of the projection and the upper surfaces of the first and second switching transistors are shielded thereby, and that the signal read line does not come in contact with the conductive layer forming the horizontal selection gate line.

What is claimed is: 
     
       1. A solid-state imaging device comprising: a plurality of photodiodes arrayed in matrix form so as to serve as a group of pixels, each of said photodiodes having a surface region of a predetermined shape and a projection, said projection having first and second portions, said first portion of said projection being located between said region and said second portion;   a vertical scanning circuit;   a horizontal scanning circuit;   a plurality of vertical selection gate lines extending from said vertical scanning circuit, each of said vertical selection gate lines being formed from a polysilicon material;   a plurality of horizontal selection gate lines extending from said horizontal scanning circuit;   a plurality of signal read lines interconnected between said photodiodes; wherein each of said pixels comprises: a first switching transistor, disposed between a corresponding one of said photodiodes and a predetermined signal read line, for performing an on/off operation in synchronism with a vertical scanning signal transmitted from said vertical scanning circuit through a respective one of said vertical selection gate lines; and   a second switching transistor for performing an on/off operation in synchronism with a horizontal scanning signal transmitted from said horizontal scanning circuit through a respective one of said horizontal selection gate lines so as to permit a pixel signal from said corresponding one of said photodiodes to be read in synchronism with signal read line scanning at a predetermined timing by said vertical scanning circuit and said horizontal scanning circuit;   said first switching transistor being formed by interconnection of a corresponding one of said vertical selection gate lines overlapping said first portion of a corresponding one of said projections; and   said second switching transistor comprising a vertically oriented gate portion made of said polysilicon material overlapping said second portion of said corresponding one of said projections;     wherein each of said horizontal selection gate lines comprises a plurality of vertically aligned ones of said gate portions serially coupled by predetermined portions of a first conductive layer, said first conductive layer being located above and insulated from a second conductive layer comprising said polysilicon material; and   said signal read lines comprising a plurality of predetermined portions of said first conductive layer, each signal read line being located so as to shield said projection and said first and second switching transistors, said signal read lines being insulated from said horizontal selection gate lines.   
     
     
       2. The solid-state imaging device of claim 1, wherein a plurality of said vertical selection gate lines and said signal read lines are provided for each output of said vertical scanning circuit. 
     
     
       3. The solid-state imaging device of claim 2, further comprising, for each of said vertical selection gate lines, a third switching transistor for connecting said vertical selection gate line to a first potential source in response to an output signal from said vertical scanning circuit, and a fourth switching transistor for connecting said vertical selection gate line to a second potential source in response to a reset signal. 
     
     
       4. The solid-state imaging device of claim 3, further comprising, for each of said vertical selection gate lines, a fifth switching transistor, having a gate connected to a respective one of said vertical selection gate lines, for connecting a respective one of said signal read lines to a respective signal output line. 
     
     
       5. The solid-state imaging device of claim 1, wherein each of said vertical selection gate lines is formed of a laminated polysilicon layer. 
     
     
       6. The solid-state imaging device of claim 1, wherein each of said signal read lines is formed of a first aluminum layer, and each of said horizontal selection gate lines is formed of a second aluminum layer. 
     
     
       7. A solid-state imaging device comprising: a plurality of photodiodes arrayed in a matrix, each of said photodiodes defining a pixel an each of said photodiodes having a surface region of a predetermined shape and a projection, said projection having first and second portions, said first portion of said projection being located between said surface region and said second portion;   a vertical scanning circuit;   a horizontal scanning circuit;   a first conductive layer located substantially parallel to and insulated from said projection of each of said photodiodes, said first conductive layer having a plurality of first linear portions and a plurality of first curved portions, said first conductive layer being formed of a polysilicon material;   a second conductive layer located substantially parallel to and insulated from said first conductive layer, said second conductive layer having a plurality of second linear portions and a plurality of second curved portions, said second conductive layer being formed from a second conductive material; wherein each of said pixels further comprises: a first switching transistor comprising a selected one of said first linear portions operatively coupled to a corresponding one of said projections at said first portion; and   a second switching transistor comprising a vertically oriented one of said first curved portions operatively coupled to a corresponding one of said projections at said second portion;     a plurality of vertical selection gate lines, each of said vertical selection gate lines comprising horizontally aligned ones of said selected first liner portions and a plurality of other first linear portions, each of said vertical selection gate lines being operatively coupled to said vertical scanning circuit;   a plurality of horizontal selection gate lines, each of said horizontal selection gate lines comprising vertically aligned ones of said selected first curved portions serially coupled to vertical ones of said second linear portions, each of said horizontal selection gate lines being operatively coupled to said horizontal scanning circuit; and   a plurality of read signal lines interconnected between said photodiodes, each of said read signal lines comprising horizontally aligned ones of said second curved portions serially coupled to a plurality of horizontal ones of said second linear portions, each of said signal read lines being located so as to electrically shield said projection and said first and second switching transistors; wherein   each of said first switching transistors is operatively coupled between a corresponding one of said photodiodes and a predetermined signal read line so as to permit an on/off operation in synchronism with a vertical scanning signal transmitted from said vertical scanning circuit through a respective one of said vertical selection gate lines; and wherein   each of said second switching transistors is operatively coupled so as to provide an on/off operation in synchronism with a horizontal scanning signal transmitted from said horizontal scanning circuit through a respective one of said horizontal selection gate lines to permit a pixel signal from said corresponding one of said photodiodes to be read in synchronism with signal read line scanning at a predetermined timing by said vertical scanning circuit and said horizontal scanning circuit.   
     
     
       8. The solid-state imaging device of claim 7, wherein a plurality of said vertical selection gate lines and said signal read lines are provided for each output of said vertical scanning circuit. 
     
     
       9. The solid-state imaging device of claim 8, further comprising, for each of said vertical selection gate lines, a third switching transistor for connecting said vertical selection gate line to a first potential source in response to an output signal from said vertical scanning circuit, and a fourth switching transistor for connecting said vertical selection gate line to a second potential source in response to a reset signal. 
     
     
       10. The solid-state imaging device of claim 9, further comprising, for each of said vertical selection gate lines, a fifth switching transistor, having a gate connected to a respective one of said vertical selection gate lines, for connecting a respective one of said signal read lines to a respective signal output line. 
     
     
       11. The solid-state imaging device of claim 7, wherein said first conducting layer comprises a laminated polysilicon layer. 
     
     
       12. The solid-state imaging device of claim 7, wherein said second conductive layer further comprises first and second aluminum layers, and wherein each of said signal read lines is formed of said first aluminum layer, and each of said horizontal selection gate lines is formed of said second aluminum layer.