Priority encoder for a content addressable memory

Abstract

A priority encoder for receiving input request signals at a number of input request terminals and for providing an N-bit output binary code word indicating the binary identification number of the highest-priority, currently-active input request terminal. Each output bit of the output binary code word is provided from a respective logic circuit. Whenever any one of a first group of input request terminals, which are identified as having a logical TRUE value in a particular bit position of the N-bit output binary code word, is active, all of a second group of input request terminals, having a logical FALSE value for the particular bit position, are disabled. Sequential operation of the logic circuits for each output bit is obtained by successively delaying enablement of a logic circuit until high-order logic circuits have completed operation.

We claim: 
     
       1. A priority encoder for receiving request signals from 2 N  input request lines and for providing an N-bit output code word which identifies the highest-priority, currently-active, input request line, comprising: 2 N  input request terminals for receiving request signals from respective input request lines, each of said 2 N  input request terminals having a successive binary identification number assigned thereto, wherein each of the 2 N  input request terminals are ranked in order of priority so that lower binary identification numbers are assigned higher priority with the lowest binary identification number having the highest priority;   N output terminals, each respectively providing one bit of an N-bit output binary code word, which indicates the binary identification number of the highest-priority, currently active input request terminal;   a plurality of N logic circuits, each of which are respectively associated with one of said N output terminals;   wherein each of said plurality of N logic circuits has input terminals which are coupled respectively to input request terminals of a first predetermined group of said input request terminals, which are identified as having a logical TRUE value in the bit position of the N-bit output binary code word associated with a particular one of said input request terminals;   wherein each of said plurality of N logic circuits also has a logic output terminal which controls each one of a second predetermined group of said 2 N  input request terminals, which are identified as being those input request terminals which have a logical FALSE value in the bit position of the N-bit output binary code word associated with a particular one of said input request terminals;   wherein said logic output terminal provides a signal for disabling the each of the input request terminals of said second group of input request terminals when one or more of said first group of input request terminals are active;   means for sequentially enabling each of said N logic circuits by, starting with the logic circuit associated with the highest order bit of the N-bit output binary code word, successively delaying enablement of the next logic circuit associated with a lower order bit until the higher-order logic circuit has completed operation.   
     
     
       2. The priority encoder of claim 1 wherein said means for sequentially enabling each of said N logic circuits includes a cascaded series of delay circuits for sequentially providing successively delayed enable signals to each of the plurality of logic circuits, with the logic circuits receiving enable signal according to the order of the N output terminals. 
     
     
       3. The priority encoder of claim 1 wherein each of said logic circuits includes pull-down transistors coupled to the input request terminals of said second group of input request terminals for disabling said second group of input request terminals when one of said first group of input request terminal is active. 
     
     
       4. The priority encoder of claim 1 wherein each of said logic circuits includes an AND gate, having an input terminal coupled to said means for sequentially enabling each of said N logic circuits and having an input terminal activated by one of said first group of input request terminals, said AND gate providing an output signal for disabling the second group of input request terminals. 
     
     
       5. A priority encoder for receiving request signals from 2 N  input request lines and for providing an N-bit output code word which identifies the currently active, highest-priority input request line, comprising: from 2.sup. N input request terminals for receiving request signals from respective input request lines, each request terminal being identified by an N-bit binary identification code word, each request terminal being coupled to a first reference voltage level through a respective pull-up resistor; N output terminals, each respectively providing one bit of an N-bit output binary identification code word identifying the currently-active request terminal with the highest priority;   each one of said N output terminals having a logic circuit associated therewith;   each of said logic circuits including means for sensing a request signal on any one of a first set of N/2 input terminals, where each of said first set of input terminals have a HIGH value in its binary identification code word for the bit corresponding to the output terminal with which a particular logic circuit is associated;   each of said logic circuits also including N/2 pull-down transistors which are respectively connected to the input terminals of a second set of N/2 inputs terminals, where each of said second set of input terminals have a LOW value in its binary identification code word for the bit corresponding to the output terminal with which a particular logic circuit is associated;   each of said logic circuits having means for operating the pull-down transistors to disable the second set of input terminals when any one of set first set of input request terminals is active;   means for sequentially enabling each of said logic circuits, starting with the logic circuit which is associated with the highest-order bit of the N-bit output binary identification code word.   
     
     
       6. The priority encoder of claim 5 wherein each logic circuit includes a plurality of pull-down transistors, each respectively having an input terminal connected to one of said first set of input terminals and each respectively having and output terminal connected to a terminal of a common pull-up resistor so that an active LOW state on any of the terminals of the first set of input terminals pulls the terminal of the pull-up resistor to a LOW state; a logic gate having a first input terminal connected to the terminal of the pull-up resistor, said logic gate having a second input terminal connected to the means for sequentially enabling each logic circuit, said logic gate having an output terminal coupled to the pull-down transistors connected to the second set of input request terminals for disabling said second set of transistors when one of said first set of input request terminals is active.