Timer circuit including an analog ramp generator and a CMOS counter

Abstract

A timer circuit provides a wide range of precise and substantially accurate time intervals. The timer circuit includes a ramp generator circuit having a first input for receiving an input signal to start a ramp signal, a second input for receiving a ramp timing conrol signal, and an output for providing a ramp signal. A comparator has a first input coupled to the output of the ramp generator, a second input coupled to a reference voltage source, and an output for providing an end ramp signal. A counter circuit has a first input for receiving the end ramp signal to begin counting, a second input for receiving a counter timing control signal, and an output for providing a terminal count signal. The end ramp signal and the terminal count signal are combined in an AND gate to provide a signal that is delayed by a predetermined amount from the input signal.

We claim: 
     
       1. A timer circuit (10) comprising: (a) a ramp generator circuit (20) having a first input for receiving an input signal, a second input for receiving a ramp timing control signal, and an output for providing a ramp signal;   (b) a comparator (50) having a first input coupled to the output of the ramp generator, a second input coupled to the reference voltage source (VREF), and an output for providing an end ramp signal representing a first time interval:   (c) a counter circuit (80) having a first input for receiving the end ramp signal, a second input for receiving a counter timer control signal, and an output for providing a terminal count signal representing a second time interval, the counter circuit counting the number of cycles of the counter timing control signal from the end ramp signal to a predetermined count; and   (d) means (100) for combining the end ramp signal and the terminal count signal to provide an output signal that is delayed by a predetermined time interval from the input signal as determined by the first and second time intervals.   
     
     
       2. A timer circuit (10) as in claim 1 in which the ramp generator circuit (20) comprises: (a) a first transistor (Q4) having a base for receiving the input signal, the input signal having first and second voltage levels, a collector coupled to a first source of supply voltage, and an emitter for receiving a first reference current;   (b) a capacitor (C4) coupled between the first source of supply voltage and the emitter of the first transistor; and   (c) a second transistor (Q27) having a base coupled to the emitter of the first transistor, a collector coupled to the first source of supply voltage, and an emitter for supplying the ramp signal and for receiving a second reference current.   
     
     
       3. A timer circuit (10) as in claim 2 in which the reference voltage source (VREF) comprises: (a) a third transistor (Q10) having a base for receiving a fixed voltage having a value between the first and second voltage levels, a collector coupled to the first source of supply voltage, and an emitter for receiving a third reference current; and   (b) a fourth transistor (Q28) having a base coupled to the emitter of the third transistor, a collector coupled to the first source of supply voltage, and an emitter for supplying the reference voltage and for receiving a fourth reference current.   
     
     
       4. A timer circuit (10) as in claim 3 in further comprising a voltage-to-current converter (30) for supplying the first, second, third, and fourth reference currents proportional to the ramp timing control voltage. 
     
     
       5. A timer circuit (10) as in claim 4 in which the voltage-to-current converter (30) comprises: (a) a bias line (44);   (b) a fifth transistor (Q40) having a collector, an emitter, and a base coupled to the bias line;   (c) a first resistor (310) having a first end coupled to the emitter of the fifth transistor and a second end for receiving the ramp timing control voltage;   (d) a current mirror (318) having an input coupled to the collector of the fifth transistor and an output;   (e) a sixth transistor (Q22) having a collector coupled to the output of the current mirror, a base coupled to the bias line, and an emitter coupled to a source of constant voltage; and   (f) seventh (Q38), eighth (Q41), ninth (Q26), and tenth (Q11) transistors each having a base coupled to the bias line, an emitter, and a collector for respectively providing the first, second, third, and fourth reference currents.   
     
     
       6. A timer circuit (10) as in claim 5 in which the voltage-to-current converter (30) further comprises: (a) a second resistor (306) having a first end coupled to the emitter of the seventh transistor and a second end for receiving the ramp timing control voltage; and   (b) a third resistor (308) having a first end coupled to the emitter of the ninth transistor and a second end for receiving the ramp timing control voltage.   
     
     
       7. A timer circuit (10) as in claim 6 in which the emitters of the eighth and tenth transistors are each coupled to the source of constant voltage. 
     
     
       8. A timer circuit (10) as in claim 5 in which the first resistor comprises first (310) and second (316) resistor components and the ramp timing control voltage comprises (Vdac) first (Vfastdac) and second (Vslowdac) ramp timing control voltage components, (a) the first resistor component having a first end coupled to the emitter of the fifth transistor and a second end for receiving the first ramp timing control voltage component, and   (b) the second resistor component having a first end coupled to the emitter of the fifth transistor and a second end for receiving the second ramp timing control voltage component.   
     
     
       9. A timer circuit (10) as in claim 5 in which the voltage-to-current converter (30) further comprises means for applying the constant voltage to the emitter of each of the seventh, eighth, ninth and tenth transistors. 
     
     
       10. A timer circuit (10) as in claim 1 in which the comparator (50) comprises: (a) a comparator stage (505) having a positive input, a negative input, and an output for providing the end ramp signal;   (b) a first buffer stage (506) having an input forming the first input of the comparator and an output coupled to the positive input of the comparator stage, the input of the first buffer stage having an associated input current;   (c) a second buffer stage (508) having an input forming the second input of the comparator and an output coupled to the negative input of the comparator stage, the input of the second buffer stage having an associated input current;   (d) a first compensation current source (502) coupled to the input of the first buffer stage having a current value substantially equal to the associated input current of the first buffer stage; and   (e) a second compensation current source (504) coupled to the input of the second buffer stage having a current value substantially equal to the associated input current of the second buffer stage.   
     
     
       11. A timer circuit (10) as in claim 10 in which the first (506) and second (508) buffer stages each comprise: (a) a transistor (Q5) having a base forming the input, a collector, and an emitter;   (b) a diode (D5) having an anode forming the output and a cathode;   (c) a bias current source (Q58) coupled to the emitter of the transistor and the cathode of the diode; and   (d) a current mirror (Q84, Q85, Q86, r84, r85) having an input coupled to the collector of the transistor and an output coupled to the anode of the diode.   
     
     
       12. A timer circuit (10) as in claim 1 in which the counter circuit (80) comprises a CMOS counter circuit. 
     
     
       13. A timer circuit (10) as in claim 12 in which the CMOS counter circuit further comprises: (a) an ECL-to-CMOS converter (60) coupled in series with the first input of the CMOS counter circuit; and   (b) a CMOS-to-ECL converter (90) coupled in series with the output of the CMOS counter circuit.   
     
     
       14. A timer circuit (10) as in claim 13 in which the ECL-to-CMOS converter (60) comprises: (a) a first Schottky diode (606) having an anode and a cathode for receiving an ECL level input, the cathode being coupled to the output of the comparator;   (b) a second Schottky diode (608) having an anode and a cathode coupled to the cathode of the first Schottky diode;   (c) a PNP transistor (614) having a base coupled to the anode of the first Schottky diode, a collector coupled to the anode of the second Schottky diode for providing a CMOS level output, and an emitter, the CMOS level output being coupled to the first input of the CMOS counter circuit;   (d) a first resistor (610) coupled between the emitter of the PNP transistor and a first source of supply voltage (28); and   (e) a second resistor (612) coupled between the collector of the PNP transistor and a second source of supply voltage (46).   
     
     
       15. A timer circuit (10) as in claim 13 in which the CMOS-to-ECL converter (90) comprises: (a) a first resistor (806) coupled between a CMOS level input and an ECL level output, the CMOS level input being coupled to the output of the CMOS counter circuit and the ECL level output providing the terminal count signal;   (b) a second resistor (804) coupled between the ECL level output and a first source of supply voltage (28); and   (c) a third resistor (808) coupled between the ECL level output and a second source of supply voltage (46).   
     
     
       16. A timer circuit (10) as in claim 12 in which the CMOS counter circuit further comprises a multiple stage flip-flop synchronizer circuit (70) coupled in series with the first input of the CMOS counter circuit. 
     
     
       17. A timer circuit (10) comprising: (a) means (20) for generating a ramp signal upon the command of an input signal;   (b) means (50) for generating an end of ramp signal when the ramp signal reaches a predetermined magnitude, wherein the difference in time between the end of ramp signal and the input signal defines a first time interval;   (c) means (80) for counting a predetermined number of clock cycles initiated by the end of ramp signal, wherein the predetermined number of cycles defines a second time interval; and   (d) means (100) for providing an output signal that is delayed from the input signal by a total time interval substantially equal to the sum of the first and second time intervals.   
     
     
       18. A method for providing a time interval to delay an output signal with respect to an input signal, the method comprising: generating a ramp signal upon the command of an input signal;   generating an end of ramp signal when the ramp signal reaches a predetermined magnitude, wherein the difference in time between the end of ramp signal and the input signal defines a first time interval;   counting a predetermined number of clock cycles in response to the end of ramp signal, wherein the predetermined number of cycles defines a second time interval; and   providing an output signal that is delayed from the input signal by a total time interval substantially equal to the sum of the first and second time intervals.   
     
     
       19. A method for providing a time interval as in claim 18, including the step of adjusting the total time interval less than a predetermined period of time by adjusting the first time interval. 
     
     
       20. A method for providing a time interval as in claim 18, including the step of adjusting the total time interval more than a predetermined period of time by adjusting one of the first and second time intervals. 
     
     
       21. A method for providing a time interval as in claim 18, including the step of disabling the counter such that the total time interval is substantially equal to the first time interval. 
     
     
       22. A method for providing a time interval as in claim 18, including the step of setting the first time interval to be greater than or equal to a time required for the counter to reset.