Method and apparatus for input-buffered asynchronous transfer mode switching

Abstract

An ATM packet switching system has output segregated input buffers, which are operated on a realtime by crosspoint selection circuits implementing a combined buffer fill/age algorithm to come up with a new selection every packet cycle.

We claim: 
     
       1. An asynchronous transfer mode (ATM) packet switching method comprising the steps of: storing all incoming data packets in order of arrival in a plurality of input packet buffers; polling all incoming data packets for their switch output port destinations; determining on a realtime basis a first plurality of data packets among data packets stored in said plurality of input packet buffers to be applied to input ports of said switch during a packet transmission cycle, following determination of said first plurality of input packets, for transmission through said switch it its output ports; applying said first plurality of data packets to said input ports, wherein the first plurality of data packets is determined by prioritizing data packets stored in said plurality of input packet buffers, and inculding only those data packets, in order or priority, in said first plurality of data packets whose output port destination differs from port destinations of data packets having a higher order of priority, and wherein the order of priority of incoming data packets is established by: measuring the fill of each of said plurality of input packet buffers; and measuring the number of transmission cycles during which no data packets have left each of said plurality of input packet buffers. 
     
     
       2. A packet switching system for cyclically interconnecting a first plurality of input-ports to a second plurality of output-ports, wherein input data packets arriving at said plurality of input ports bear information identifying their output destinations, comprising: a third plurality of input-port packet storage buffers, each having a fourth plurality of independent first-in-first-out (FIFO) packet storage buffers; and said second and fourth pluralities are equal in number and bear fixed assignment relationship on a one-to-one basis to each other irrespective of cyclical interconnections between said first and second pluralities. 
     
     
       3. A packet switching apparatus comprising: a switch having a plurality of independent input ports and a plurality of independent output ports, said switch cyclically reconfigurable in response to switch control means; a plurality of independent input packet storage buffers, one each of cyclically applying a data packet to each one of said plurality of independent input ports; a cyclically updated memory map for storing preddetermined satrus indicia of said plurality of independent input packet storage buffers; and means for cyclically applying said status indicia to said switch control means to reconfigure it.