Pipeline circuit for timing adjustment of irregular valid and invalid data

Abstract

A pipeline circuit is capable of adjusting the timing of data, in a data processing system for ensuring processing, even if the input timings of different data are irregular or the input data are invalid. This is achieved by generating a selection signal, which is input to a data holding circuit. The selection signal determines the particular register in which a datum is stored. The value of the selection signal is determined by an input indicating signal, which indicates whether a particular datum is valid or invalid. When the data is valid the selection signal is shifted to the next value, indicating the next higher register, and when the data is invalid the selection signal maintains the value it had for the previous datum.

What is claimed is: 
     
       1. A pipeline circuit for determining a data holding duration in said circuit based on the validity or invalidity of data, comprising: (a) a selection signal generating means for generating a selection signal S j  in response to an input indicating signal T j  for every corresponding input data A j , J=1, . . . m, where m is an integer, said input indicating signal T j  having a first state indicating validity and a second state indicating invalidity of said input data A j ,   (b) a data holding circuit including a plurality of data holding means R 1  . . . R n , n being an integer, connected in a pipelined manner for storing at least some of said input data A j , and for transferring valid data stored in one of said data holding means R p , to a next one of said data holding means in series to R p+1 , . . . R n ,   (c) wherein said selection signal generating means is operative when said input indicating signal T j  indicates validity of said corresponding input data A j  for maintaining said selection signal S j  at a value of a previous selection signal S j-1 , and operative when said input indicating signal T j  indicates invalidity of said corresponding input data A j  for indicating a value of said selection signal S j  equal to the next value in a periodic set of values 1, 2, . . . n, 1, 2, . . . following a value equal to said value of said previous selection signal S j-1 .   
     
     
       2. A pipeline circuit as recited in claim (1), wherein said m input indicating signal T j  is further inputted into said data holding circuit and said data holding means R j  store said input indicating signal T j  with said corresponding input data A j  and, said data holding circuit simultaneously outputs said input indicating signal T j  and said corresponding input data A j . 
     
     
       3. A pipeline circuit as in claim (1), wherein said selection signal generating means receives a selection signal initial value S0, and an initial value setting indicating signal ST j , where if V means validity and I means invalidity then the following holds,   ______________________________________                                    
T.sub.j  ST.sub.j          S.sub.j                                        
______________________________________                                    
V        V                 SO                                             
V        I                 S.sub.j-1                                      
I        V                 SO                                             
I        I                 S.sub.j-1 ± 1                               
______________________________________                                    
     
     
     
       4. A pipeline circuit as described in claim (1), wherein said input indicating signal T j  is inputted to each of said data holding means R i . 
     
     
       5. A pipeline circuit as described in claim (1), which further includes, an indicating means holding circuit with n-1 stages of indicating signal holding means F j , which has said input indicating signal T j  and said selection signal S j  as inputs and which outputs an output indicating signal V j , with m values V 1 , V 2 , . . . , V m , where, if said selection signal S j  is n, then V j  =T j , and,   if said selection signal S j  is i<n, then said input indicating signal T j  is stored in said indicating signal holding means F j  and outputted via n-i-1 stages of said indicating signal holding means F i+1 , F i+2 , . . . , F n-1  as the output indicating signal V j , n-i timing cycles later than the inputting of said input indicating signal T j , and wherein, said data holding circuit receives said output indicating signal V j  and is operative in response thereto such that   if said selection signal S j  is i(i<n) and if said output indicating signal V j  indicates validity or invalidity then said corresponding input data A j  is outputted via n-i-1 stages of said data holding means R i+1 , R i+2 , . . . , R n , n-i timing cycles later,   if said selection signal S j  is n and if said output indicting signal V j  indicates validity, then said corresponding input data A j  is stored in said data holding means R n  and is outputted one timing cycle later, and   if said selection signal, S j  is n and if said output indicating signal V j  indicates invalidity, then said corresponding input data A j  is not stored in said data holding means R n .   
     
     
       6. A pipeline circuit as described in claim 5, wherein said indicating signal holding circuit has an additional indicating signal holding means F n , which outputs a signal H j  corresponding to said input data A j  indicating the validity or invalidity of said input data A j  as said input data A j  is outputted from said data holding circuit. 
     
     
       7. A pipeline circuit as in claim 5, wherein a selection signal initial value SO, and an initial value setting indicating signal ST j  are inputted to said selection signal generating means where, if said input indicating signal T j  and said initial value indicating signal ST j  indicate invalidity, then said selection signal S j  =S j-1  ±1 and if said input indicating signal T j  indicates validity, and said initial value setting indicating signal ST j  indicates invalidity, then said S j  =S j-1 , and   if said input indicating signal T j  indicates invalidity and said initial value setting indicating signal ST j  indicates validity, then said S j  equals said initial value SO,   if said initial value setting indicating signal ST j  and said input indicating signal T j  indicate validity, then said selection signal S j  is said initial value SO.   
     
     
       8. A pipeline circuit as described in claim (7), wherein said indicating signal holding circuit has an additional indicating signal holding means F n , which outputs a signal H j  corresponding to said input data A j  indicating the validity or invalidity of said input data A j  as said input data A j  is output from said data holding circuit. 
     
     
       9. A pipeline circuit for determining a data holding duration in said circuit based on the validity or invalidity of data, comprising: a selection signal generating circuit for outputting a selection signal S j  indicating a value, said value indicated by said selection signal S j  being equal to a next value in a periodic sequence of n values (1, 2, . . . n, 1, 2, . . . ) following the value in said periodic sequence which was indicated by a preceding selection signal S j-1  when an input indicating signal T j , corresponding to one datum A j  out of a series of m input data A 1 , A 2 , . . . , A m  indicates invalidity, and, said value indicated by said selection signal S j  being equal to the same value as that indicated by said preceding selection signal S j-1  when said input indicating signal T j  indicates validity; and   a data holding circuit including a plurality of data holding means R 1  . . . R n  (where n is an integer) connected in a pipelined manner, said data holding circuit coupled to said selection signal generating circuit such that said datum A j  is inputted into a data holding means R i  of said data holding means, the i-th among n stages of data holding means R 1 , R 2 , . . . , R n  when said value indicated by said selection signal S j  generated by said selection signal generating circuit is i, and outputting via n-i stage of data holding means R i+1 , R i+2 , . . . , R n  of said data holding means the datum A j , n-i+1 (where i>n, n is an integer) timing cycles later than the inputting of the data A j  where   said m input data A 1 , A 2 , . . . , A j , . . . , A m  and said m input indicating signals T 1 , T 2 , . . . , T j , . . . , T m  are entered, and where valid data among said m input data are successively outputted at n×k+1 (k is an integer) timing cycles.   
     
     
       10. A pipeline circuit, as claimed in claim 9, wherein the same units of information as said m input indicating signals T 1 , T 2 , . . . , T m  are entered into said data holding circuit as part of said m input data A 1 , A 2 , . . . , A m . 
     
     
       11. A pipeline circuit for determining a data holding duration in said circuit based on the validity or invalidity of data, comprising: a selection signal generating circuit for outputting a selection signal S j  indicating a value, said value indicated by said selection signal S j  being equal to a next value in a periodic sequence of n values (1, 2, . . . n, 1, 2, . . . ) following the value in said periodic sequence which was indicated by a preceding selection signal S j-1  when an input indicating signal T j , corresponding to one datum A j  out of a series of m input data A 1 , A 2 , . . . , A m  indicates invalidity, and, said value indicated by said selection signal S j  being equal to the same value as that indicated by said preceding selection signal S j-1  when said input indicating signal T j  indicates validity; and   a data holding circuit including a plurality of data holding means R 1  . . . R n  (where n is an integer) connected in a pipelined, having as inputs said datum A j , said data holding circuit coupled to said selection signal generating circuit such that said selection S j  corresponding to said datum A j  and said input indicating signal T j , which, if said value indicated by said selecting signal S j  is i, inputs said datum A j  and said input indicating signal T j  into a data holding means R i  of said data holding means, the i-th among n stages of data holding means R 1 , R 2 , . . . , R n , and which outputs, via n-i stages of data holding means R i+1 , R i+2 , . . . , R n  of said data holding means, the datum A j  n-i+1 (where i<n, n is an integer) timing cycles later than the inputting of the datum A j , if said input indicating signal T.sub. j indicates validity, and invalidating said datum A j  when said input indicating signal T j  indicates invalidity where   said m input data A 1 , A 2 , . . . , A j , . . . , A m  and said m input indicating signals T 1 , T 2 , . . . , T j , . . . , T m  respectively corresponding to said input data are entered, and where valid data among said input data are successively outputted at n×k+1 (k is an integer) timing cycles.   
     
     
       12. A pipeline circuit for determining a data holding duration in said circuit based on the validity or invalidity of data, comprising: a selection signal generating circuit for outputting a selection signal S j  indicating a value, said value indicated by said selection signal S j  being equal to a next value in a periodic sequence of n values (1, 2, . . . n, 1, 2, . . . ) following the value in said periodic sequence which was indicated by a preceding selection signal S j-1  when an input indicating signal T j , corresponding to one datum A j  out of a series of m input data A 1 , A 2 , . . . , A m  indicates invalidity, and, said value indicated by said selection signal S j  being equal to the same value as that indicated by said preceding selection signal S j-1  when said input indicating signal T j  indicates validity; and   an indicating signal holding circuit coupled to said selection signal generating circuit for outputting an output indicating signal V j  =T j  when said value indicated by the selection signal S j  from said selection signal generating circuit, corresponding to an inputting of said input indicating signal T j , and said selection signal S j  is i (i<n, n is an integer), said input indicating signal T j  is inputted to indicating signal holding means F i , the i-th among n-1 stages of said indicating holding means F 1 , F 2 , . . . , F n-1 , and outputted via an n-i-1 stage of said indicating signal holding means F i+1 , F i+2 , . . . , F n-1  as the output indicating signal V j , n-i timing cycles later than said inputting of said input indicating signal T j  ; and   a data holding circuit including a plurality of data holding means R 1  . . . R n  (where n is an integer) connected in a pipelined manner, coupled to said selection signal generating circuit and said indicating signal holding circuit for inputting said datum A j  to data holding means R i  of said data holding means, the i-th among n stages of data holding means R 1 , R 2 , . . . , R n , of said data holding means when said value indicated by said selection signal S j  corresponding to said datum A j , said selection signal S j  and said output indicating signal V j , are i (i<n), said data A j  being conveyed as a datum P via an n-i-1 stage of said data holding means R i+1 , R i+2 , . . . , R n , n-i timing cycles later than said inputting of said datum A j , but when said value indicated by said selection signal S j  is n, conveying said datum A j , as said datum P to said n-th data holding means R n  and, when said output indicating signal V j  indicates invalidity, invalidating the input to said n-th data holding means R n  or, when said output indicating signal V j  indicates validity, conveying said datum P to said n-th data holding means R n  and outputting said datum P one timing cycle later where   said m input data A 1 , A 2 , . . . , A j , . . . , A m  and said m input indicating signals T 1 , T 2 , . . . , T j , . . . , T m  respectively corresponding to said input data are entered, and where valid data among said m input data are successively outputted at n×k+1 (k is an integer) timing cycles.