Normalization estimator

Abstract

A normalization circuit (24) which comprises a signed digit subtracter (25) coupled to operand registers (14, 19). The signed digit subtracter (25) subtracts the operands and inputs a signed digit difference to a pseudovalue converter (27). The pseudovalue converter (27) generates a pseudovalue in non-redundant format which contains its most significant non-zero bit in the selected bit position. The pseudovalue is output to a leading zero counter (28) which counts the number of leading zeroes in the pseudovalue.

What is claimed is: 
     
       1. A normalization circuit for normalizing a result of an arithmetic operation performed on a first and second operands by a computational circuit, comprising: a signed digit subtracter operable to subtract the first operand from the second operand, and output a difference;   a pseudovalue converter having an input coupled to said output of said signed digit subtracter, said pseudovalue converter operable to convert said difference into pseudovalue; and   a leading zero counter coupled to receive said pseudovalue and operable to count the number of leading zeroes in said pseudovalue.   
     
     
       2. The normalization circuit of claim 1 wherein said normalization circuit is coupled in parallel with said computational circuit. 
     
     
       3. The normalization circuit of claim 1 wherein said pseudovalue converter is operable to generate said pseudovalue such that said pseudovalue contains a number of leading zeroes equal to or one less than the number of leading zeroes in said result of said arithmetic operation. 
     
     
       4. The normalization circuit of claim 1 wherein said pseudovalue converter is operable to perform a three bit overlapped scan on said difference to identify predetermined three bit patterns indicative of the approximate location of the most significant nonzero bit in said result. 
     
     
       5. The normalization circuit of claim 1 wherein the arithmetic operation comprises subtraction. 
     
     
       6. The normalization circuit of claim 1 wherein one of the operands is selectively denormalized prior to performing the arithmetic operation such that exponents associated with the operands are equal. 
     
     
       7. A method of normalizing a result of an arithmetic operation of two floating point operands comprising the steps of: performing a signed digit subtraction on said floating point operands to yield a signed digit difference in a signed digit subtractor;   transmitting signals associated with the signed digit difference to a pseudovalue converter;   converting the signed digit difference to a non-redundant pseudovalue having a number of zeroes within a predetermined range of the number of zeroes in the result of the arithmetic operation in the pseudovalue converter; and   counting the number of zeroes in the pseudovalue to yield an estimation of the number of leading zeroes in the results of the arithmetic operation in a leading zero counter.   
     
     
       8. The method of claim 7, and further comprising the step of: shifting the result of the arithmetic operation a number of bit positions equal to the estimation to yield an intermediate result.   
     
     
       9. The method of claim 8 and further comprising the step of conditionally shifting the intermediate result a single bit position responsive to the state of the most significant bit in the intermediate result to yield a normalized result. 
     
     
       10. The method of claim 7 wherein the arithmetic operation comprises subtraction. 
     
     
       11. The method of claim 7 wherein one of the operands is denormalized prior to performing the arithmetic operation such that exponents associated with the operands are equal.