Phase locked loop having constant gain for recovering clock from non-uniformly spaced data

Abstract

A constant loop gain phase lock loop for recovering a clock from non-uniformly spaced data pulses utilizes a programmable current source and charge pump whereby the current into the charge pump is proportional to the number of VCO clock periods between data pulses. As the time between pulses increases the current charging the pump increases and when the time between pulses decreases the current charging the pump decreases to maintain a constant loop gain independent of the data pattern.

What is claimed is: 
     
       1. A phase locked loop oscillator comprising a voltage controlled oscillator for generating a clock having a frequency which is proportional to an applied voltage,   a phase comparator for receiving and comparing phases of data pulses and said clock and generating a phase comparison signal indicative of said clock leading or lagging said data pulses in phase,   counter means for receiving said clock and said data pulses and generating a count of clock cycles between data pulses,   a current to voltage convertor for converting a current to a voltage for controlling said voltage controlled oscillator,   a variable current source for applying a current to said current to voltage convertor, the magnitude of said current being proportional to said count, said current being positive into said convertor when said clock is lagging said data pulses in phase and being negative when said clock is leading said data pulses in phase, and   means for applying said voltage from said current to voltage convertor to said voltage controlled oscillator as a control voltage.   
     
     
       2. A phase locked loop oscillator comprising a voltage controlled oscillator for generating a clock having a frequency which is proportional to an applied voltage,   a phase comparator having two inputs for receiving data pulses and said clock from said voltage controlled oscillator and having a first output when said clock is lagging said data pulses and a second output when said clock is leading said data pulses,   a variable current source for generating a control current,   counter means for receiving said clock and said data pulses and generating a count of clock cycles between data pulses,   means for applying said count to said variable current source whereby said control current is proportional to said count,   a current to voltage convertor for converting a current to a voltage,   means for applying a charging current to said current to voltage convertor, the magnitude of said charging current being proportional to the magnitude of said control current, said charging current being positive when said clock is lagging said data pulses, and said charging current being negative when said clock is leading said data pulses, and   means for applying the voltage from said current to voltage convertor to said voltage controlled oscillator as a controlled voltage.   
     
     
       3. In a phase locked loop circuit, a charge pump for use in obtaining a control voltage for a voltage controlled oscillator which generates a clock in response to data pulses comprising a current to voltage convertor,   counter means for receiving said clock and said data pulses and generating a count of clock cycles between data pulses, and   a variable current source for applying a current to said current to voltage convertor, the magnitude of said current being proportional to said count, said current being positive into said convertor when said clock is lagging said data pulses in phase and being negative away from said convertor when said clock is leading said data pulses in phase.