Semiconductor memory device and manufacturing method thereof

Abstract

Disclosed is a semiconductor memory device having such a structure that a voltage variation on a bit line does not affect a voltage on another bit line. A gate electrode portion branches and extends laterally from a word line and extends almost in parallel with the bit line. First and second impurity regions of a field effect transistor are formed on regions between adjacent word lines, with the gate electrode portion therebetween. A capacitor electrically connected to the second impurity region is formed to cover the bit lines. Since the capacitor is between adjacent bit lines, no voltage variation on one bit line affects a voltage on the other bit lines.

What is claimed is: 
     
       1. A semiconductor memory device comprising: a semiconductor substrate having a main surface;   a word line formed on said main surface;   a field effect transistor including a first impurity region formed in said main surface, a second impurity region formed in said main surface, spaced apart from said first impurity region to form a channel region, and a gate electrode portion made of a material different from the material of said word line, said gate electrode portion formed on said main surface and extending laterally from said word line to overlap said channel region;   a bit line formed on said main surface to be electrically connected to said first impurity region, said bit line crossing said word line at a different level above the substrate; and   a capacitor including a first electrode layer electrically connected to said second impurity region, and a second electrode layer facing said first electrode layer with a dielectric therebetween,   at least one electrode layer of said capacitor electrostatically shielding said bit line.   
     
     
       2. The semiconductor memory device in accordance with claim 1, wherein the material of said word line has a lower resistance value than the material of said gate electrode portion.   
     
     
       3. The semiconductor memory device in accordance with claim 2, wherein the material of said word line comprises aluminum, and the material of said gate electrode portion comprises polysilicon.   
     
     
       4. The semiconductor memory device in accordance with claim 1, wherein said word line is positioned higher than said gate electrode portion, and   said word line and said gate electrode portion are electrically connected by a conductive member.   
     
     
       5. The semiconductor memory device in accordance with claim 4, wherein said conductive member comprises tungsten or molybdenum formed by a selective CVD method.   
     
     
       6. A semiconductor memory device comprising: a semiconductor substrate having a main surface;   a word line formed on said main surface;   a field effect transistor including a first impurity region formed in said main surface, spaced apart from said first impurity region to form a channel region, and a gate electrode portion, said gate electrode portion formed on said main surface and extending laterally from said word line to overlap said channel region;   a bit line formed on said main surface to be electrically connected to said first impurity region, said bit line crossing said word line at a different level above the substrate; and   a capacitor including a first electrode layer electrically connected to said impurity region, and a second electrode layer facing said first electrode layer with a first dielectric therebetween,   at least one of said first and second electrode layers being formed at an equal level to or at a higher level than the level of said bit line formed on said main surface,   wherein a plurality of said word lines are provided on said main surface, and said first and second impurity region are provided between adjacent said word lines.   
     
     
       7. The semiconductor memory device in accordance with claim 6, wherein said gate electrode portion and said bit line extended in parallel.   
     
     
       8. The semiconductor memory device in accordance with claim 6, wherein a direction from said first impurity region to said second impurity region is in parallel with an extending direction of said word lines.   
     
     
       9. The semiconductor memory device in accordance with claim 6, wherein an interconnection layer is formed above said word line, and   said word line and said interconnection layer are electrically connected with each other.   
     
     
       10. The semiconductor memory device in accordance with claim 6, wherein said second electrode layer overlaps said bit line.   
     
     
       11. The semiconductor memory device in accordance with claim 6, wherein said first electrode layer overlaps said bit line.   
     
     
       12. The semiconductor memory device in accordance with claim 10, wherein said first electrode layer overlaps a portion of said bit line, and   a second dielectric is provided between said first electrode layer and said bit line and between said second electrode layer and said bit line.   
     
     
       13. The semiconductor memory device in accordance with claim 12, wherein said second dielectric comprises a silicon oxide film.   
     
     
       14. A semiconductor memory device comprising: a semiconductor substrate having a main surface;   a word line formed on said main surface;   a field effect transistor including a first impurity region formed in said main surface, a second impurity region formed in said main surface, spaced apart from said first impurity region to form a channel region, and a gate electrode portion, said gate electrode portion formed on said main surface and extending laterally from said word line to overlap said channel region;   a bit line formed on said main surface to be electrically connected to said first impurity region, said bit line crossing said word line at a different level above the substrate; and   a capacitor including a first electrode layer electrically connected to said second impurity region, and a second electrode layer facing said first electrode layer with a first dielectric therebetween,   at least one of said first and second electrode layers being formed at an equal level to or at a higher level than the level of said bit line formed on said main surface,   wherein said word line is positioned higher than said gate electrode portion, and said word line and said gate electrode portion are electrically connected by a conductive member.   
     
     
       15. The semiconductor memory device in accordance with claim 14, wherein a material of said word line has a lower resistance value than a material of said gate electrode portion.   
     
     
       16. A semiconductor memory device comprising: a semiconductor substrate having a main surface;   a word line formed on said main surface;   a field effect transistor including a first impurity region formed in said main surface, a second impurity region formed in said main surface, spaced apart from said first impurity region to form a channel region, and a gate electrode portion, said gate electrode portion formed on said main surface and extending laterally from said word line to overlap said channel region;   a bit line formed on said main surface to be electrically connected to said first impurity region, said bit line crossing said word line at a different level above the substrate; and   a capacitor including a first electrode layer electrically connected to said second impurity region, and a second electrode layer facing said first electrode layer with a first dielectric therebetween,   wherein a plurality of said word lines are provided on said main surface, and said first and second impurity regions are provided between adjacent said word lines.   
     
     
       17. A semiconductor memory device comprising: a semiconductor substrate having a main surface;   a word line formed on said main surface;   a field effect transistor including a first impurity region formed in said main surface, a second impurity region formed in said main surface, spaced apart from said first impurity region to form a channel region, and a gate electrode portion, said gate electrode portion formed on said main surface and extending laterally from said word line to overlap said channel region;   a bit line formed on said main surface to be electrically connected to said first impurity region, said bit line crossing said word line at a different level above the substrate; and   a capacitor including a first electrode layer electrically connected to said second impurity region, and a second electrode layer facing said first electrode layer with a first dielectric therebetween,   wherein said word line is positioned higher than said gate electrode portion, and said word line and said gate electrode portion are electrically connected by a conductive member.   
     
     
       18. The semiconductor memory device in accordance with claim 14, wherein said gate electrode portion and said bit line extend in parallel.   
     
     
       19. The semiconductor memory device in accordance with claim 14, wherein a direction from said first impurity region to said second impurity region is in parallel with an extending direction of said word line.   
     
     
       20. The semiconductor memory device in accordance with claim 14, wherein a material of said word line has a lower resistance value than a material of said gate electrode portion.   
     
     
       21. The semiconductor memory device in accordance with claim 14, wherein an interconnection layer is formed above said word line, and   said word line and said interconnection layer are electrically connected with each other.   
     
     
       22. The semiconductor memory device in accordance with claim 14, wherein said second electrode layer overlaps said bit line.   
     
     
       23. The semiconductor memory device in accordance with claim 14, wherein said first electrode layer overlaps said bit line.   
     
     
       24. The semiconductor memory device in accordance with claim 20, wherein said first electrode layer overlaps a portion of said bit line, and   a second dielectric is provided between said first electrode layer and said bit line.   
     
     
       25. The semiconductor memory device in accordance with claim 24, wherein said second dielectric comprises a silicon oxide film.   
     
     
       26. A semiconductor memory device comprising: a semiconductor substrate having a main surface;   a word line formed on said main surface;   a field effect transistor including a first impurity region formed in said main surface, a second impurity region formed in said main surface, spaced apart from said first impurity region to form a channel region, and a gate electrode portion, said gate electrode portion branching laterally from said word line to overlap said channel region;   a bit line formed on said main surface to be electrically connected to said first impurity region, said bit line crossing said word line at a different level above the substrate; and   a capacitor including a first electrode layer electrically connected to said second impurity region, and a second electrode layer facing said first electrode layer with a first dielectric therebetween,   at least one of said first and second electrode layers being formed at an equal level to or at a higher level than the level of said bit line formed on said main surface, wherein   a direction from the first impurity region to the second impurity region is in parallel with an extending direction of said word line.   
     
     
       27. A semiconductor memory device comprising: a semiconductor substrate having a main surface;   a word line formed on said main surface;   a field effect transistor including a first impurity region formed in said main surface, a second impurity region formed in said main surface, spaced apart from said first impurity region to form a channel region, and a gate electrode portion, said gate electrode portion branching laterally from said word line to overlap said channel region;   a bit line formed on said main surface to be electrically connected to said first impurity region, said bit line crossing said word line at a different level above the substrate; and   a capacitor including a first electrode layer electrically connected to said second impurity region, and a second electrode layer facing said first electrode layer with a first dielectric therebetween,   at least one of said first and second electrode layers being formed at an equal level to or at a higher level than the level of said bit line formed on said main surface, wherein   a material of said word line has a lower resistance value than a material of said gate electrode portion.   
     
     
       28. The semiconductor memory device in accordance with claim 16, wherein said gate electrode portion and said bit line extend in parallel.   
     
     
       29. The semiconductor memory device in accordance with claim 16, wherein a direction form said first impurity region to said second impurity region is in parallel with an extending direction of said word lines.   
     
     
       30. The semiconductor memory device in accordance with claim 23, wherein a material of said word line has a lower resistance value than a material of said gate electrode portion.   
     
     
       31. The semiconductor memory device in accordance with claim 15, wherein an interconnection layer is formed above said word line, and   said word line and said interconnection layer are electrically connected with each other.   
     
     
       32. The semiconductor memory device in accordance with claim 16, wherein said second electrode layer overlaps said bit line.   
     
     
       33. The semiconductor memory device in accordance with claim 16, wherein said first electrode layer overlaps said bit line.   
     
     
       34. The semiconductor memory device in accordance with claim 32, wherein said first electrode layer overlaps a portion of said bit line, and   a second dielectric is provided between said first electrode layer and said bit line.   
     
     
       35. The semiconductor memory device in accordance with claim 34, wherein said second dielectric comprises a silicon oxide film.   
     
     
       36. The semiconductor memory device in accordance with claim 17, wherein said gate electrode portion and said bit line extend in parallel.   
     
     
       37. The semiconductor memory device in accordance with claim 17, wherein a direction from said first impurity region to said second impurity region is in parallel with an extending direction of said word line.   
     
     
       38. The semiconductor memory device in accordance with claim 17, wherein a material of said word line has a lower resistance value than a material of said gate electrode portion.   
     
     
       39. The semiconductor memory device in accordance with claim 17, wherein an interconnection layer is formed above said word line, and   said word line and said interconnection layer are electrically connected with each other.   
     
     
       40. The semiconductor memory device in accordance with claim 17, wherein said second electrode layer overlaps said bit line.   
     
     
       41. The semiconductor memory device in accordance with claim 17, wherein said first electrode layer overlaps said bit line.   
     
     
       42. The semiconductor memory device in accordance with claim 40, wherein said first electrode layer overlaps a portion of said bit line, and   a second dielectric is provided between said first electrode layer and said bit line.   
     
     
       43. The semiconductor memory device in accordance with claim 42, wherein said second dielectric comprises a silicon oxide film.   
     
     
       44. A semiconductor memory device comprising: a semiconductor substrate having a main surface;   a word line formed on said main surface;   a field effect transistor including a first impurity region formed in said main surface, a second impurity region formed in said main surface, spaced apart from said first impurity region to form a channel region, and a gate electrode portion, said gate electrode portion branching out laterally from said word line to overlap said channel region;   a bit line formed on said main surface to be electrically connected to said impurity region, said region, said bit line crossing said word line at a different level above the substrate; and   a capacitor including a first electrode layer electrically connected to said second impurity region, and a second electrode layer facing said first electrode layer with a first dielectric therebetween, wherein   a direction from said first impurity region to said second impurity region is in parallel with an extending direction of said word line.   
     
     
       45. A semiconductor memory device comprising: a semiconductor substrate having a main surface;   a word line formed on said main surface;   a field effect transistor including a first impurity region formed in said main surface, a second impurity region formed in said main surface, spaced apart from said first impurity region to form a channel region, and a gate electrode portion, said gate electrode portion branching out laterally from said word line to overlap said channel region;   a bit line formed on said main surface to be electrically connected to said impurity region, said region, said bit line crossing said word line at a different level above the substrate; and   a capacitor including a first electrode layer electrically connected to said second impurity region, and a second electrode layer facing said first electrode layer with a first dielectric therebetween, wherein   a material of said word line has a lower resistance value than a material of said gate electrode portion.