High electron mobility transistor with GaN/Alx Ga1-x N heterojunctions

Abstract

A high electron mobility transistor is disclosed, which takes advantage of the increased mobility due to a two dimensional electron gas occurring in GaN/Al x Ga 1-x N heterojunctions. These structures are deposited on basal plane sapphire using low pressure metalorganic chemical vapor deposition. The electron mobility of the heterojunction is aproximately 620 cm 2 per volt second at room temperature as compared to 56 cm 2 per volt second at 180° K. and decreased to 19 cm 2 per volt second at 77° K. The mobility for the heterostructure, however, increased to a value of 1,600 cm 2 per volt second at 77° K. and saturated at 4° K.

I claim: 
     
       1. A transistor, comprising: (a) a substrate;   (b) a buffer, the buffer being deposited on the substrate;   (c) a first active layer, the first active layer being composed essentially of GaN, the first active layer being deposited on the buffer;   (d) a second active layer, the second active layer being composed essentially of Al x  Ga 1-x  N, where x is greater than 0 and less than 1; and   (e) a plurality of electrical connections, the electrical connections residing on the second active layer, the plurality of electrical connections comprising: (i) a source connection, the source connection residing on the second active region;   (ii) a gate connection, the gate connection residing on the second active region;   (iii) a drain connection, the drain connection residing on the second active region;      thereby permitting a difference of electrical potential to be applied to the second active region so as to permit operation as a transistor.   
     
     
       2. The transistor of claim 1, wherein the source connection is formed by depositing a layer of gold on the second active region. 
     
     
       3. The transistor of claim 2, wherein the gate connection is defined on the second active region by forming a layer of metal, the metal being composed essentially of a metal chosen from a group including gold, silver, aluminum, and indium. 
     
     
       4. The transistor of claim 3, wherein the drain connection is formed by depositing a metal layer on the second active region, the metal layer being chosen from a group consisting of gold, silver, aluminum and indium. 
     
     
       5. The transistor of claim 4, wherein the first active region has a thickness of between 500 and 2,000 angstroms. 
     
     
       6. The transistor of claim 5, wherein the substrate is composed essentially of a material chosen from a group including silicon, gallium arsenide, silicon carbide, aluminum oxide and indium phosphide. 
     
     
       7. The transistor of claim 6, wherein the buffer layer is composed essentially of aluminum nitride. 
     
     
       8. The transistor of claim 7, wherein the buffer layer has a thickness of between 25 and 75 angstroms. 
     
     
       9. The transistor of claim 8, wherein the second active region has a thickness of between 450 and 550 angstroms. 
     
     
       10. The transistor of claim 9, wherein the transistor may operate satisfactorily at a temperature of greater than 100° C. 
     
     
       11. The transistor of claim 10, wherein the electron mobility being greater than 1,000 cm 2  per volt second. 
     
     
       12. The transistor of claim 11, wherein x is approximately equal to 0.15.