Electrostatic discharge voltage protection circuit for a solid state instrument

Abstract

A protection circuit for a solid state instrument includes a plurality of fuses and a switching device arranged in parallel with the input capacitance of the solid state instrument, The fuses protect the instrument from high voltage surges, and the switching device protects the instrument from lower voltage surges. The fuses and the switching device are solid state devices and thus can be fabricated along with the solid state instrument.

What is claimed is: 
     
       1. A protection circuit having an input line and a ground line for protecting a solid state instrument from electrostatic discharges comprising: a plurality of solid state fusing devices arranged in parallel between said input line and said ground line, the input capacitance of said solid state instrument also being arranged between said input line and said ground line, said fusing devices protecting said instrument from electrostatic discharges above a minimum voltage;   a solid state switching device arranged in parallel with said input capacitance for shunting currents produced by electrostatic discharges below said minimum voltage; and   a resistor in combination with said input capacitance, said resistor having a value whereby the RC time constant of said resistor and said input capacitance is higher than the switching time of said fusing devices and said switching device.   
     
     
       2. The protection circuit of claim 1 wherein said fusing devices are amorphous silicon devices. 
     
     
       3. The protection circuit of claim 2 wherein said solid state switching device is an amorphous silicon thin film transistor. 
     
     
       4. The protection circuit of claim 3 wherein said thin film transistor has a floating gate. 
     
     
       5. The protection circuit of claim 4 wherein said solid state instrument is a liquid crystal display device. 
     
     
       6. The protection circuit of claim 1 wherein said solid state fusing devices are arranged in a single solid state strip, and wherein said solid state fusing devices are amorphous silicon devices.   
     
     
       7. The protection circuit of claim 6 wherein said solid state switching device is an amorphous silicon thin film transistor. 
     
     
       8. The protection circuit of claim 7 wherein said solid state instrument is a liquid crystal display device. 
     
     
       9. A protection circuit including a plurality of parallel fusing devices each of said fuzes comprising: an insulative substrate; a first layer of Si 3  N 4  overlying one surface of said substrate;   a second layer of undoped semiconductor material overlying said first layer;   a third layer of doped semiconductor material overlying said second layer;   a conductive electrode overlying said third layer;   a channel, having a dimension L, extending through said conductive electrode and said third layer and extending partially through said second layer, whereby the bottom of said channel lies within the distance d of said first layer; and   a fourth layer of Si 3  N 4  overlying said third layer and said channel.   
     
     
       10. The protection circuit of claim 9 wherein said fusing devices are arranged in a single solid state strip, and wherein said dimension L is selected such that said fusing devices are protection against electrostatic discharges above a minimum voltage. 
     
     
       11. The protection circuit of claim 10 wherein said thin film transistor is protection against electrostatic discharges below said minimum voltage. 
     
     
       12. The protection circuit of claim 11 wherein said semiconductor material is amorphous silicon. 
     
     
       13. The protection circuit of claim 9 wherein said semiconductor material is amorphous silicon. 
     
     
       14. A solid state fusing device comprising: an insulative substrate;   a first layer of Si 3  N 4  overlying one surface of said substrate;   a second layer of undoped semiconductor material overlying said first layer;   a third layer of doped semiconductor material overlying said second layer;   a conductive electrode overlying said third layer;   a channel, having a dimension L, extending through said conductive electrode and said third layer and extending partially through said second layer, whereby the bottom of said channel lies within the distance d of said first layer; and   a fourth layer of Si 3  N 4  overlying said third layer and said channel.   
     
     
       15. The device of claim 14 wherein said dimension L is selected such that said fusing devices are protection against electrostatic discharges above a minimum voltage. 
     
     
       16. The solid state fusing device of claim 14 wherein said semiconductor material is amorphous silicon.