Method of making a MOS thin film transistor with self-aligned asymmetrical structure

Abstract

A semiconductor thin film formed over a substrate and having drain and source regions each being of a conductivity type and a channel region of another conductivity type defined between the drain and source regions, a gate electrode(s) formed over and/or below the channel region of the semiconductor thin film through an insulating layer(s), a pair of electrodes being connected to the drain and source regions of the semiconductor thin film, in which said source region is placed in a self-aligned manner and adjoined to said channel region, while a drain-offset region is defined between said channel region and said drain region in a self-aligned manner.

What we claimed is: 
     
       1. A method of making a thin film transistor having a self-aligned asymmetrical structure, said method comprising: forming a semiconductor thin film over a substrate, said thin film being formed to include a drain region, a channel region and a partial source region, said drain and partial source regions being of one conductivity type and said channel region being of another conductivity type;   forming a gate electrode over said channel region and a pair of electrodes including a drain electrode and a source electrode, said drain electrode being concurrently formed with the formation of said gate electrode by the same layer forming said gate electrode, whereby a drain-offset region is formed between said gate electrode and drain electrode;   completing the formation of the source region in a self-aligned manner by ion implantation using said source electrode and gate electrode as a mask.   
     
     
       2. A method as in claim 1, said method further comprising: forming a second gate on said substrate prior to forming said semiconductor thin film over said substrate.   
     
     
       3. A method as in claim 1 in which said semiconductor thin film has a thickness of 20 to 60 nm. 
     
     
       4. A method as in claim 1, wherein an ion is implanted in low concentration in said drain-offset region using said gate electrode and drain electrode as a mask after completing the formation of the source region. 
     
     
       5. A method as in claim 1, wherein said drain-offset region is formed between said channel region and said drain region in a self-aligned manner by ion implantation using said gate and drain electrodes as a mask. 
     
     
       6. A method as in claim 1, wherein said source is formed concurrently with the formation of said gate electrode and drain electrode by the same layer forming said gate electrode and drain electrode. 
     
     
       7. A method as in claim 1, wherein said drain-offset region is covered with a mask upon completing the formation of the source region. 
     
     
       8. A method as in claim 7, wherein said drain-offset region is of the same conductivity type as said drain region. 
     
     
       9. A method as in claim 7, wherein said drain-offset region is of the same conductivity type as said channel region.