Digital communication electrical/optical access node having buffer memory matrix for switchable multi-channel bidirectional transmission
Abstract
The network access node of a digital communication system for the bidirectional transmission of message signals between, for example, a switching center and subscribers as an electrically switchable connection between the lines to the switching centers with a first interface and the lines to the subscribers with a second interface. The first interface is preferably an interface for a time-division multiplex signal with a transmission rate of 2 Mbit/s; the second interface is preferably an interface for signals in multiple access with time-division multiplex (TDM/TDMA). The buffer memory of the TDM/TDMA system is made up of partial memories arranged as a matrix. The partial memories are used simultaneously as a buffer memory for the circuit of the paths.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1. Network electrical/optical access node of a digital communication system for two-way transmission of message signals between first equipment, and second equipment, wherein a first type of lines electrically couples the first equipment with a first bidirectional interface of the network access node for transmitting time-division multiplexed message signals at a first lower bit rate in a time-division multiplex hierarchy, wherein a second type of lines optically couples the second equipment with a second bidirectional interface of the network access node for transmitting the message signals at a second higher bit rate in a time-division multiple access hierarchy, wherein a separate multiplexer/demultiplexer means is provided at each respective first and second bidirectional interface, one multiplexer/demultiplexer means being responsive to the message signals at the first lower bit rate, for providing multiplexed message signals, and vice versa, and the other multiplexer/demultiplexer means being responsive to the message signals at the second higher bit rate, for providing demultiplexed message signals, and vice versa, characterized in that transmission paths between the first and second types of lines are switchable in the network access node, a buffer memory is responsive to the multiplexed message signals and the demultiplexed message signals from the respective separate multiplexer/demultiplexer means, the buffer memory having addressable partial memories for storing the message signals, for switching the transmission paths between the first and second types of lines during communication in both directions between the first and second equipment, and for forming the time-division multiplex message signals, and the buffer memory is located between the separate multiplexer/demultiplexer means.
2. A network access node as claimed in claim 1, characterized in that the buffer memory includes a first portion and a second portion each having a plurality of addressable partial memories and the partial memories are arranged in the form of a matrix, and that the partial memories of each row of the matrix are connected in parallel to one input of the buffer memory, and the partial memories of each column of the matrix are connected in parallel to one output of the buffer memory, or vice versa.
3. A network access node as claimed in claim 2, characterized in that the matrix has additional addressable partial memories associated therewith for generating a preamble for message signals.
4. A network access node as claimed in claim 2, characterized in that in the first portion of the buffer memory, the message signals to be transmitted in a downstream direction are stored, and that in the second portion, the message signals to be transmitted in an upstream direction are stored and data multiplexing and demultiplexing are performed.
5. A network access node as claimed in claim 3, characterized in that the addressable partial memories comprise a number of addressable memory locations which corresponds to a specific number of time windows per time frame of the time-division multiplexed message signals.
6. A network access node as claimed in claim 2, characterized in that channels are addressed between the first and second equipment by a counter, and message signals are read from the partial memories by a table connected to the counter.
7. A network access node as claimed in claim 6, characterized in that the table represents the memory of a microprocessor.
8. A network access node as claimed in claim 2, characterized in that in the first portion, the partial memories of each column of the matrix, which are connected in parallel with one of the outputs, have an additional parallel-connected partial memory associated therewith for carrying out the frame formation of the time-division multiplexed message signals.
9. A network access node as claimed in claim 2, characterized in that in the second portion, partial memories of each row of the matrix, which are connected in parallel with one of the outputs, have an additional parallel-connected partial memory associated therewith, and that partial memories of each column of the matrix, which are connected in parallel with one of the inputs, have an additional parallel-connected partial memory associated therewith for carrying out the frame formation of the time-division multiplexed message signals.
10. A network access node according to claim 1, characterized by the fact that each partial memory has a memory capacity of one byte.
11. A network access node according to claim 1, characterized in that 64 partial memories are combined on an integrated memory chip.
12. A network access node according to claim 1, characterized in that, between the network access node and first equipment there is coupled an adaptation circuit for changing the transmission rate, and optionally if analog signals are present, carries out an analog-digital transformation.
13. A network access node according to claim 4, characterized in that message signals are transmitted in the downstream direction with a time-division multiplex process, and message signals are transmitted in the upstream direction with a time-division multiple access process.Cited by (0)
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