Serial accessible semiconductor memory device

Abstract

The semiconductor memory device includes a serial memory cell array and an input-output circuit. The input-output circuit includes first and second latch circuits, first and second transfer circuits and an output circuit. The first transfer circuit transfers the information read from the serial memory cell array to the first latch circuit. The second transfer circuit transfers the information from the first latch circuit 103 to the second latch circuit 105. The output circuit externally supplies as output the information held in the second latch circuit. A clock generator supplies a clock signal to the first and the second transfer circuits and the output circuit so that the output operation by the output circuit may be effected, and then the transfer operation by the first transfer circuit may be effected after the transfer by the second transfer circuit has been effected.

What is claimed is: 
     
       1. A semiconductor memory device, comprising: storing means for storing a plurality of information;   read means for serially reading the information stored in said storing means;   first holding means for holding the information read by said read means;   second holding means for holding the information supplied from said first holding means;   first transfer means for transferring the information read by said read means to said first holding means;   second transfer means for transferring the information from said first holding means to said second holding means;   output means for externally supplying as output the information held in said second holding means; and   control means for effecting control so that after the transfer by said second transfer means has been effected, an output operation by said output means may be effected, and then the transfer by said first transfer means may be effected.   
     
     
       2. The semiconductor memory device according to claim 1, wherein said control means generates a second activation signal for activating said second transfer means, then a first activation signal for activating said output means, and then a third activation signal for activating said first transfer means. 
     
     
       3. The semiconductor memory device according to claim 2, wherein said first transfer means includes a first inverter circuit responsive to said first activation signal to become active, and said second transfer means includes a second inverter circuit responsive to said second activation signal to become active.   
     
     
       4. The semiconductor memory device according to claim 1, wherein said first holding means includes a latch circuit, and said second holding means includes a latch circuit.   
     
     
       5. The semiconductor memory device according to claim 1, wherein said output means comprises: third holding means for holding information;   switch means connected between said second holding means and said third holding means, responsive to said third activation signal to become conductive; and   output circuit for externally supplying as output the information held in said third holding means.   
     
     
       6. The semiconductor memory device according to claim 1, wherein said storing means includes a plurality of memory cells arranged in a column, and said read means includes serial selector means responsive to an externally applied address signal for sequentially selecting said plurality of memory cells.   
     
     
       7. A dual port memory, comprising: a first memory cell array including a plurality of memory cells arranged in a matrix;   first selecting means for randomly selecting any of the plurality of memory cells in said first memory cell array for writing or reading of information;   first input-output means for supplying externally applied information to said first memory cell array or externally supplying as output the information read from said first memory cell array;   a second memory cell array including a plurality of memory cells arranged in a row;   second selecting means for sequentially selecting the plurality of memory cells in said second memory cell array for writing or reading of information;   second input-output means for supplying externally applied information to said second memory cell array or externally supplying as output the information read from said second memory cell array;   transfer means for transferring the information between one row in said first memory cell array and said second memory cell array; and   control means for controlling said second input-output means,   said second input-output means including: first holding means for holding the information read form said second memory cell array;   second holding means for holding the information supplied from said first holding means;   first transfer means for transferring the information read from said second memory cell array to said first holding means;   second transfer means for transferring the information from said first holding means to said second holding means;   output means for externally supplying as output the information held in said second holding means; and   said control means for effecting control so that after the transfer by said second transfer means has been effected, the output operation by said output means may be effected, and then the transfer by said first transfer means may be effected.     
     
     
       8. The dual port memory according to claim 7, wherein said first selecting means comprises: row selecting means for selecting any of the plurality of rows in said first memory cell array for writing or reading of information; and   column selecting means for selecting any of the plurality of columns in said first memory cell array for writing or reading of information.   
     
     
       9. The dual port memory according to claim 7, wherein each of the plurality of memory cells in said first memory cell array includes a dynamic type memory cell, and each of the plurality of memory cells in said second memory cell array includes a static type memory cell.   
     
     
       10. The dual port memory according to claim 7, wherein said control means controls said second input-output means in response to an externally applied clock signal. 
     
     
       11. An operating method of a semiconductor memory device comprising storing means for storing a plurality of information and first and second holding means for holding information, comprising the steps of: serially reading the information stored in said storing means;   transferring the information from said first holding means to said second holding means,   then externally supplying as output the information held in said second holding means; and then   transferring the information read from said storing means to said first holding means.