Multi-chip solid-state image sensing device

Abstract

The solid-state image sensing device comprises N-piece photodiodes (2 i ) for converting optical signals to electric signals; N-piece buffers (3 i ) for detecting the converted electric signals, respectively; a shift register having a plurality of series-connected transfer stages (8 i ) for generating a read pulse (9 i ) on the basis of a control pulse (8 i ) at a predetermined timing and transmitting another control pulse (8 i+ ) to the succeeding stage at another predetermined timing, respectively; a dummy transfer stage (6 0 ) of the same structure as the shift register transfer stages, for transmitting a control pulse (8 1 ) to the first shift register transfer stage in response to an external control pulse (8 0 ) at another predetermined timing; a common output line (10); and N-piece select gates (5 i ) for outputting a detection signal of the buffer (3 i ) to the common output line on the basis of the read pulse (9 i ), respectively. Since control pulses (8 i ) applied to the respective transfer stages (6 i ) of the shift register can be generated internally from the dummy transfer stage and the preceding transfer stages of the shift register of the same structure, the waveforms of the control pulses can be equalized, thus improving the S/N ratio of the detected image signals.

What is claimed is: 
     
       1. A multi-chip solid-state image sensing device, comprising: an integrated output line; and   a plurality of (L(≧2)) of solid-state image sensing chips arranged in series, an i-th (i=1, 2, . . . L) solid-state image sensing chip comprising   N(≧2) photoelectric sensing elements for converting optical signals to electric signals;   N signal detecting means for detecting an electric signal from the corresponding photoelectric sensing elements, respectively;   transfer means having a shift register with (N+1) series-connected transfer stages, for generating a read pulse on the basis of a control pulse and for transferring the control pulse to a succeeding transfer stage, respectively;   dummy transfer means having m (m≧1) transfer stages and having the same structure as that of the transfer stages of said shift register, for transmitting the control pulse received from a previous (i-1) the solid-state image sensing chip to a first transfer stage of the i-th solid-state image sensing chip in response to the control pulse;   N switching means for outputting a detection output of an i-th signal detecting means to a common output line, respectively on the basis of the read pulse transmitted from an i-th transfer stage of said shift register; and   applying means for applying a pulse in phase with the control pulse transmitted from a (N-m)th transfer stage of the shift register of the i-th (i=1, . . . L-1) solid-state image sensing chip to a first stage of the transfer means of an (i+1)the solid-state image sensing chip as a control input,   wherein said integrated output line integratedly outputs signals outputted from the respective common output line of the solid-state image sensing chips.