Pipeline circuit

Abstract

A pipeline circuit adopted for a CPU or a microprocessor in a computer system, computes the effective branch destination address of a conditional branch instruction before or in parallel with the execution of the conditional branch instruction, judges according to a result of the execution of an instruction just before the conditional branch instruction whether or not a branch condition of the conditional branch instruction is met, and, if the branch condition is met, executes the conditional branch instruction while prefetching and decoding an instruction located at the branch destination address.

What is claimed is: 
     
       1. An information processing system for processing instructions according to a pipeline circuit, comprising: an instruction fetching unit for fetching an instruction from a memory;   an instruction decoding unit connected to said fetching unit for decoding an instruction transferred from said fetching unit;   an execution unit connected to said decoding unit for executing the instruction decoded by said decoding unit; and   an address generating unit connected to said decoding unit and said fetching unit for calculating an effective address of the decoded instruction in response to an address calculation request transferred from said decoding unit; wherein   said fetching unit includes a program counter for storing an address of an instruction to be fetched from said memory and an instruction buffer for storing a fetched instruction, said address generating unit being connected to said instruction buffer for calculating said effective address based on a displacement transferred from said instruction buffer when said displacement is used for the address calculation;   said address generating unit starting calculation of a branch destination address when a conditional branch instruction has been decoded by said decoding unit;   said branch destination being held by said address generating unit if it is not determined whether or not the branch condition is satisfied after said branch destination address is calculated by said address generating unit;   when it is determined that the branch condition is satisfied, the branch destination address being set in said program counter so that the fetching operation of said branch destination instruction is carried out;   when it is determined that the branch condition is not satisfied, said branch destination address not being set in said program counter so that the fetching operation of said branch destination instruction is not carried out; and   when it is determined that the branch condition is not satisfied before completion of the calculation of said branch destination address, said branch destination address calculation is continued up to the end.   
     
     
       2. The pipeline circuit in a computer system as claimed in claim 1, in which a reading operation of instructions stored in the instruction buffer is controlled by a pointer which indicates a position of a data to be read next and is advanced by one word whenever a data is read out of the instruction buffer according to a readout request from said instruction decoding unit or from said effective address generating unit. 
     
     
       3. The pipeline circuit in a computer system as claimed in claim 1, in which the branch destination address of the conditional branch instruction is computed even if it is found, before said effective address generating unit computes the effective branch destination address of the conditional branch instruction, that the branch condition of the conditional branch instruction is not met. 
     
     
       4. The information processing system as claimed in claim 1 wherein said execution unit is connected with said address generating unit through said instruction decoding unit.