Floating gate non-volatile memory blocks and select transistors

Abstract

A non-volatile memory device is described. The memory device includes a global bit line, a first block, and a second block. The first block includes a first memory cell having a drain region, a source region, a floating gate and a control gate. A first word line is coupled to the control gate of the first memory cell. A first local bit line is coupled to the drain region of the first memory cell. A first selecting means couples the first local bit line to the global bit line. The second block includes a second memory cell having a drain region, a source region, a floating gate and a control gate. A second word line is coupled to the control gate of the second memory cell. A second local bit line is coupled to the drain region of the second memory cell. A second selecting means couples the second local bit line to the global bit line.

What is claimed is: 
     
       1. A non-volatile memory device comprising: (A) a global bit line;   (B) a first block comprising (1) a first memory cell having a drain region, a source region, a floating gate, and a control gate;   (2) a first word line coupled to the control gate of the first memory cell;   (3) a first local bit line coupled to the drain region of the first memory cell;   (4) a first transistor for coupling the first local bit line to the global bit line, wherein the first transistor has a drain coupled to the global bit line and a source coupled to the first local bit line, wherein the gate of the transistor is selectable between an off potential and an on potential; and     (C) a second block comprising (1) a second memory cell having a drain region, a source region, a floating gate, and a control gate;   (2) a second word line coupled to the control gate of the second memory cell;   (3) a second local bit line coupled to the drain region of the second memory cell;   (4) a second transistor for coupling the second local bit line to the global bit line, wherein the second transistor has a drain coupled to the global bit line and a source coupled to the second local bit line, wherein the gate of the second transistor is selectable between an off potential and an on potential.     
     
     
       2. The memory device of claim 1, further comprising a block select decoder coupled to the gate of the first and second transistors for selecting a selected block of the first and second block by applying the on potential to the gate of one of the first and second transistors of the selected block. 
     
     
       3. The memory device of claim 1, wherein the on potential is above +5 volts and the off potential is ground. 
     
     
       4. The memory device of claim 1, wherein the first transistor is N-channel field-effect transistor and the second transistor is N-channel field-effect transistor. 
     
     
       5. The memory device of claim 1, wherein the source region for the first memory cell is connected through a diffusion layer to a first common source line that is formed by a first metal layer connected to the diffusion layer, wherein the source region for the second memory cell is connected through a diffusion layer to a second common source line that is formed by a first metal layer connected to the diffusion layer, wherein both the first and the second common source line is coupled to a source and block select decoder. 
     
     
       6. A non-volatile memory device comprising: (A) a global word line;   (B) a first block comprising (1) a first memory cell having a drain region, a source region, a floating gate and a control gate;   (2) a first local word line coupled to the control gate of the first memory cell;   (3) a first bit line coupled to the drain region of the first memory cell;   (4) a first transistor for coupling the first local word line to the global word line, wherein the first transistor has a drain coupled to the global word line and a source coupled to the first local word line, wherein the gate of the transistor is selectable between an off potential and an on potential; and     (C) a second block comprising (1) a second memory cell having a drain region, a source region, a floating gate and a control gate;   (2) a second local word line coupled to the control gate of the second memory cell;   (3) a second bit line coupled to the drain region of the second memory cell;   (4) a second transistor for coupling the second local word line to the global word line, wherein the second transistor has a drain coupled to the global word line and a source coupled to the second local word line, wherein the gate of the second transistor is selectable between an off potential and an on potential.     
     
     
       7. The memory device of claim 6, further comprising a block select decoder coupled to the gate of the first and second transistors for selecting a selected block of the first and second block by applying the on potential to the gate of one of the first and second transistors of the selected block. 
     
     
       8. The memory device of claim 6, wherein the on potential is above +5 volts and the off potential is ground. 
     
     
       9. The memory device of claim 6, wherein the first transistor is N-channel field-effect transistor and the second transistor is N-channel field-effect transistor. 
     
     
       10. The memory device of claim 6, wherein the source region for the first memory cell is connected through a diffusion layer to a first common source line that is formed by a first metal layer connected to the diffusion layer, wherein the source region for the second memory cell is connected through a diffusion layer to a second common source line that is formed by a first metal layer connected to the diffusion layer, wherein both the first and the second common source line is coupled to a source and block select decoder.