M-dimensional computer memory with m-1 dimensional hyperplane access

Abstract

An m-dimensional memory with m-1 dimensional hyperplane access. Random access memory (RAM) circuits are arranged in a plurality of groups for storing data words corresponding to vertices of an m-dimensional lattice. Each vertex of the lattice is defined by an m-tuple. The minimum number of RAM circuits required to realize the memory architecture of the present invention is based upon the size of the lattice and the distribution of the data words in memory is based upon the m-tuples used to define the lattice.

What is claimed is: 
     
       1. An m-dimensional computer memory in which each L-bit data word corresponds to an m-tuple within an m-dimensional lattice space, and in which m-1 dimensional hyperplane access is available for any 1-tuple hyperplane request, comprising: memory means for storing said data words, said memory means comprising random access memory (RAM) circuits arranged in n m-1  groups where n is equal to the number of data words in any of the m dimensions, each of said RAM circuits storing 1-bit and each of said n m-1  groups having L RAM circuits corresponding to said L-bit data word at a distinct RAM circuit address within each of said n m-1  groups wherein, based upon said 1-tuple hyperplane request, a data word from each of the n m-1  groups is simultaneously accessed as specified by n m-1  address pairs, each of said address pairs specifying one of said n m-1  groups and one RAM circuit address within said specified group;   bus interface control mens electrically connected to said memory means for routing said simultaneous access to said RAM circuits based upon said n m-1  address pairs;   address generation means electrically connected to said bus interface control mens for generating each of said n m-1  address pairs from each of the said data words' m-tuple, said address generation means comprising a processor controlled by an operating system of instructions executed by said processor, wherein said processor generates said specified group according to a group control instruction ##EQU4##  and generates said RAM circuit address according to an address control instruction ##EQU5##  wherein t 1  is the first coordinate, t m  is the m-th coordinate and t i+1  is the (i+1) coordinate in each of said m-tuples; and   input/output (I/O) control means electrically connected to said address generation means for receiving a 1-tuple hyperplane request and for determining all m-tuples associated with said 1-tuple hyperplane request whereby said data words are arranged in said memory means to be accessible in m-1 dimensional hyperplanes, wherein said processor receives, from said I/O control means, said all m-tuples associated with said 1tuple hyperplane request and generates said specified group and RAM circuit address associated with each of said all m-tuples.   
     
     
       2. An m-dimensional computer memory as in claim 1 wherein said RAM circuits are single port RAM circuits. 
     
     
       3. An m-dimensional computer memory as in claim 1 further comprising C repetitions of said memory means electrically connected in series with one another wherein said processor generated RAM circuit address is increased by n(C-1). 
     
     
       4. A method for accessing an m-dimensional computer memory in which each L-bit data word corresponds to an m-tuple within an m-dimensional lattice space, and in which m-1 dimensional hyperplane access is available for any 1-tuple hyperplane request, comprising the steps of: storing said data words in a memory means, said memory means including random access memory (RAM) circuits arranged in n m-1  groups where n is equal to the number of data words in any of the m-dimensions, each of said RAM circuits storing 1-bit and each of said n m-1  groups having L RAM circuits corresponding to said L-bit data word at a distinct RAM circuit address within each of said n m-1  groups wherein, based upon said 1-tuple hyperplane request, a data word from each of the n m-1  groups is simultaneously accessed as specified by n m-1  address pairs, each of said address pairs specifying one of said n m-1  groups and one RAM circuit address within said specified group;   determining all m-tuples associated with said 1-tuple hyperplane request;   generating said specified group according to a group control instruction ##EQU6## generating said RAM circuit address according to an address control instruction ##EQU7## wherein t 1  is the first coordinate, t m  is the m-th coordinate and t i+1  is the (i+1) coordinate in each of said m-tuples; and   accessing said memory means based upon said generated address pairs.