Waveform equalizing filter unit

Abstract

A waveform equalizing filter unit includes a waveform equalizing filter with a plurality of taps each having a unitary delay element and a coefficient multiplier, a clock switching circuit for selecting a clock signal from at least two different frequencies, with the selected clock signal being fed to each of the unitary delay elements of the waveform equalizing filter, and a control circuit for selectively switching the tap coefficients of the coefficient multiplier in the waveform equalizing filter based upon which one of the different clock signals has been selected. A signal time adjuster is further included in a stage situated before the waveform equalizing filter that receives the input signal prior to being fed to the waveform equalizing filter to adjust the timing of the input signal in synchronism with the operation of selecting one of the different clock signal frequencies.

What is claimed is: 
     
       1. A waveform equalizing filter unit for producing an equalized output signal from an input signal to be equalized, comprising: a waveform equalizing filter realized by a plurality of unitary delay elements connected in series and having a plurality of taps connected respectively to a plurality of coefficient multipliers, the input signal to be equalized is applied to a first one of said plurality of unitary delay elements, each coefficient multiplier having a respective tap coefficient associated therewith, and an adder connected to said plurality of coefficient multipliers for combining outputs thereof to realize the equalized output signal;   a clock switching circuit having two clock signals of different respective frequencies input thereto for selecting one of said clock signals and outputting the selected clock signal to each of the unitary delay elements of said waveform equalizing filter; and   control means for determining an error in said equalized output signal relative to a predetermined ideal impulse response characteristic stored in said control means, for controlling said clock switching circuit to select one of said two clock frequencies to minimize said error, and for controlling the respective tap coefficients of said plurality of coefficient multipliers in said waveform equalizing filter upon selection of one of said two clock frequencies by said clock switching circuit and further including, in a stage situated before said waveform equalizing filter, a signal timing adjuster having an input receiving the input signal to be equalized and an output connected to said first one of said plurality of unitary delay elements for adjusting the timing of the input signal to be equalized and being controlled by said control means in synchronism with the operation of said clock switching circuit.   
     
     
       2. A waveform equalizing filter unit for producing an equalized output signal from an input signal to be equalized, comprising: a waveform equalizing filter realized by a plurality of unitary delay elements connected in series and having a plurality of taps connected respectively to a plurality of coefficient multipliers, the input signal to be equalized is applied to a first one of said plurality of unitary delay elements, each coefficient multiplier having a respective tap coefficient associated therewith, and an adder connected to said plurality of coefficient multipliers for combining outputs thereof to realize the equalized output signal;   a clock switching circuit having two clock signals of different respective frequencies input thereto for selecting one of said clock signals and outputting the selected clock signal to each of the unitary delay elements of said waveform equalizing filter; and   control means for determining an error in said equalized output signal relative to a predetermined ideal impulse response characteristic stored in said control means, for controlling said clock switching circuit to select one of said two clock frequencies to minimize said error, and for controlling the respective tap coefficients of said plurality of coefficient multipliers in said waveform equalizing filter upon selection of one of said two clock frequencies by said clock switching circuit and wherein said clock switching circuit comprises a plurality of individual switches, a corresponding individual switch being associated with each of the unitary delay elements of said waveform equalizing filter and said plurality of switches being controlled by said control means so as to connect one of the two clock frequencies to each of the unitary delay elements.