Dual port video memory system having pulse triggered dual column addressing

Abstract

Read column conductors and write column conductors of a memory array are addressed by respective triggerable sequential pulse generators which, upon receiving respective trigger pulses, provide respective read and write address pulses to respective column conductors of the array. Data to be stored is written in parallel to cells of the memory a column at a time at a rate determined by the write sequential pulse generator and is recovered a column at a time at a rate determined by the read sequential pulse generator. Advantageously, (1) the ratio of the read and write rates may be selected to provide time compression, time expansion or constant delay of video data; (2) additionally data may be written and read concurrently without bus contention and (3) addressing is simplified by a timed application of trigger pulses to the pulse generators whereby there is no need for application to the memory of binary addressing data.

What is claimed is: 
     
       1. A dual port memory system, comprising: a memory array including two row conductors for each row of cells and two column conductors for each column of cells, each cell having a first terminal connected to a data input row conductor, a second terminal connected to data output row conductor, a third input connected to a write address column conductor and a fourth input connected to a read address column conductor;   input means for applying data to be stored to said data input row conductors;   output means for recovering data stored from said data output row conductors;   a first triggerable sequential pulse generator having a trigger input terminal and a plurality of output terminals coupled to said write address column conductors and being responsive to a write trigger pulse applied to said trigger input terminal for sequentially applying cell address signals to said write address column conductors at a first predetermined rate;   a second triggerable sequential pulse generator having a trigger input terminal and a plurality of output terminals coupled to said read address column conductors and being responsive to a read trigger pulse applied to said trigger input terminal for sequentially applying cell read address signals to said read address column conductors at a second predetermined rate; and   a control signal generator for generating said read and write trigger pulses in a timed relationship.   
     
     
       2. A dual port memory system as recited in claim 1 wherein for compression of data said second predetermined rate is greater than said first predetermined rate. 
     
     
       3. A dual port memory system as recited in claim 1 wherein for providing constant delay of data said predetermined rates are equal. 
     
     
       4. A dual port memory system as recited in claim 1 wherein for providing expansion of data said second predetermined rate is less than said first predetermined rate.