Output control circuit having continuously variable drive current

Abstract

In an output circuit for an integrated circuit memory, the current drawn by output transistors is lower at high V CC voltage range than at nominal V CC . Maximum current is drawn at the low end of the V CC voltage range.

I claim: 
     
       1. An output circuit for an integrated circuit memory designed to operate over a range of power supply voltages including a nominal voltage and a high voltage, the output circuit comprising: a data receiving circuit connected to receive a data signal to be output from the memory;   a data output circuit having an output node and an output transistor having first, second, and control terminals,   the control terminal being responsively coupled to said data receiving circuit,   said first terminal being connected to receive the power supply voltage,   said second terminal being coupled to said output node; and   a circuit providing a derived power supply voltage to said data receiving circuit, said derived power supply voltage being a function of the power supply voltage,   the data receiving circuit, the circuit providing a derived power supply voltage, and the data output circuit being configured so that current drawn through said output transistor is higher at said nominal voltage than at said high voltage, and wherein the output circuit is configured to drive said output node with an output current that varies continuously in accordance with continuous changes in the power supply voltage over said range.   
     
     
       2. The circuit of claim 1 wherein said output transistor is an n-channel field effect having a drain electrode coupled to receive the power supply voltage, a source electrode providing an output signal to said output node, and a gate electrode coupled to rise in voltage in accordance with said derived power supply voltage and the state of the data applied to said data receiving circuit. 
     
     
       3. The circuit of claim 1 wherein said circuit for providing the derived power supply voltage comprises: an input for receiving a reference voltage;   an input for receiving the power supply voltage;   an internal node for developing a voltage based on the power supply voltage and the reference voltage; and   a first transistor responsively coupled to said internal node and coupled to receive the power supply voltage and providing said derived power supply voltage.   
     
     
       4. The circuit of claim 3 wherein said circuit for providing the derived power supply voltage further includes second and third transistors each having source-drain paths, the source-drain path of said second transistor coupling the power supply voltage to said internal node, the source-drain path of said third transistor coupling said internal node to another power supply voltage, said second and third transistors being sized with respect to each other so that the voltage developed at the internal node rises faster than the power supply voltage rises. 
     
     
       5. An output circuit for an integrated circuit memory designed to operate over a range of power supply voltages including a nominal power supply voltage and a high power supply voltage, the output circuit comprising: a data receiving circuit;   a data output circuit having an output transistor responsively coupled to said data receiving circuit, the data output circuit including an output node connected to said output transistor, the output circuit being configured so that current drawn through said output transistor is higher at said nominal voltage than said high voltage, and wherein said output node current varies continuously in accordance with continuous changes in the power supply voltage over said range;   a circuit providing a derived power supply voltage to said data receiving circuit, said derived power supply voltage being a function of the power supply voltage so that said output transistor draws less current at the high power supply voltage than at said nominal power supply voltage;   said data receiving circuit comprising first and second inverters, each coupled to receive the derived power supply voltage and a data input signal, said first inverter having an output coupled to the gate electrode of said output transistor, said second inverter having an output; and   a network of transistors and resistors configured to decrease peak current, said second inverter output being coupled to gate electrodes of said network transistors directly and through said resistors, said output transistor and said network being coupled at said output node.   
     
     
       6. The circuit of claim 5 wherein said network comprises first and second transistors having source, drain, and gate electrodes, the gate electrode of the first transistor being coupled to the output of the second inverter, a resistor being coupled between the gate electrodes of said first and second transistors, the source-drain path of said first and second transistors being coupled to said output node. 
     
     
       7. The circuit of claim 5 wherein said network comprises a plurality of transistors having their drain electrodes coupled in common, their source electrodes coupled in common, and their gate electrodes coupled in series via respective resistors, said plurality of transistors including n-channel transistors, said output node being coupled to the drains of said n-channel transistors. 
     
     
       8. The circuit of claim 7 wherein the transistors within said network comprise only n-channel transistors. 
     
     
       9. An output circuit for an integrated circuit memory designed to operate over a range of power supply voltages including a nominal voltage and a high voltage received from a power supply voltage source, the output circuit comprising: an output node providing the data output;   a pull-up transistor having a source-drain path coupled to said output node and to the power supply voltage source;   a pull-down transistor coupled between said output node and a reference potential; p1 a data receiving circuit coupled to receive data signals from the memory corresponding to the output signal to be developed at the output node;   a circuit providing a derived power supply voltage to said data receiving circuit, the derived power supply voltage being a function of the power supply voltage;   said pull-up transistor and said pull-down transistor each having a respective gate electrode coupled to said data receiving circuit;   said circuit providing the derived power supply voltage cooperating with said data receiving circuit so that the rise time on the gate electrode of said pull-up or pull-down transistor is higher at nominal voltage than at said higher voltage so that more current is drawn through said pull-up or pull-down transistor at the nominal voltage than at the high voltage.   
     
     
       10. The circuit of claim 9 wherein said pull-up transistor is sized for maximum current at said nominal voltage. 
     
     
       11. The circuit of claim 9 wherein said pull-up transistor comprises an n-channel transistor. 
     
     
       12. The circuit of claim 9 wherein said pull-down transistor comprises a network of transistors and resistors, the resisters coupling together the gate electrodes of the transistors of the network. 
     
     
       13. A method of providing a data output in an integrated circuit memory designed to operate over a range of power supply voltages extending to a high voltage and including a nominal voltage, comprising the steps of: receiving data at an input circuit in accordance with which an output node is to be driven;   generating a derived power supply voltage based on the actual power supply voltage and applying the derived power supply voltage to the input circuit, so that the input circuit provides a signal that is a function of the derived power supply voltage and the received data,   the derived power supply voltage changing more rapidly than variations of the actual power supply voltage within the range, said generating step including controlling a current drawn at an internal node in accordance with the derived power supply voltage so that less current is drawn at the high power supply voltage value than at the nominal voltage value;   controlling at least one output transistor of an output sage with said signal provided by the input circuit, while applying the power supply voltage to the output stage; and   developing the output signal at the output node in accordance with the current drawn on the internal node and the data received at the input circuit.   
     
     
       14. The method of claim 13 wherein said step of generating a derived power supply voltage includes continuously varying the derived power supply voltage in response to continuous changes over said range of power supply values. 
     
     
       15. An output circuit for an integrated circuit memory designed to operate over a range of power supply voltages including a minimum specified voltage, a nominal voltage and a high voltage, the output circuit comprising: an input circuit coupled to receive the data on which a data output signal is to be based, the input circuit being configured to draw more current at the nominal power supply voltage than at the higher voltage, the input circuit providing a modified data signal;   an output driver circuit powered by the power supply voltage and coupled to receive the modified data signal from said input circuit, wherein said output driver circuit provides the data output signal, said data output signal varying continuously in accordance with variations over said range of power supply voltage.   
     
     
       16. The circuit of claim 15 wherein said output driver circuit includes an output transistor having a current path coupled to the power supply voltage, said output transistor being sized for maximum current at the minimum specified voltage. 
     
     
       17. An output circuit for an integrated circuit memory comprising: an output node providing the data output;   a pull-up transistor having a source-drain path coupled to said output node and to a first power supply voltage;   a pull-down transistor coupled between said output node and a second power supply voltage;   a data receiving circuit coupled to receive data signals from the memory corresponding to the output signal to be developed at the output node;   a network of resistor sand transistors having source, drain, and gate electrodes, the gate electrode of each network transistor being coupled to said data receiving circuit, at least one of said resistors being coupled between adjacent gate electrodes of said network transistors the source-drain path of each of said transistors being coupled to said output node.   
     
     
       18. The circuit of claim 17 wherein said network transistors have their drain electrodes coupled in common, their source electrodes coupled in common, and their gate electrodes coupled together by respective said resistors, said plurality of transistors including n-channel transistors, said output node being coupled to the drains of said n-channel transistors. 
     
     
       19. The circuit of claim 18 wherein said network transistors comprise only n-channel transistors. 
     
     
       20. An output circuit for an integrated circuit memory operable over a range of power supply voltages including a nominal voltage and a high voltage, the output circuit comprising: a voltage-modifying circuit coupled to receive a reference voltage and said power supply voltage, configured to provide a derived voltage related to the power supply voltage;   an input circuit coupled to receive said derived voltage from said voltage-modifying circuit, and coupled further to receive a data signal, the input circuit providing a modified data signal that is based on at least the data signal and the derived voltage;   an output transistor and an output node and the power supply voltage, a control electrode of said output transistor being responsively coupled to said modified data signal from said input circuit.   
     
     
       21. The circuit of claim 20 wherein said input circuit comprises an inverter coupled to receive said derived voltage and said data signal and to drive an inverter output, in accordance with the logic state of the data signal, between said derived voltage and another voltage, the inverter output being said modified data signal. 
     
     
       22. The circuit of claim 20 wherein said input circuit further includes a further inverter, the circuit further comprising a further output transistor having a source-drain path coupled between said output node and a second power supply voltage, the further inverter having an input coupled to receive a complementary data signal, the further inverter having an output coupled to said further output transistor. 
     
     
       23. An output circuit for an integrated circuit memory operable over a range of power supply voltages including a nominal voltage and a high voltage, the output circuit comprising: a voltage-modifying circuit coupled to receive a reference voltage and said power supply voltage, configured to provide a derived voltage related to the power supply voltage;   an input circuit coupled to receive said derived voltage from said voltage-modifying circuit, and coupled further to receive a data signal;   an output transistor and an output node, a source-drain path of the output transistor being coupled to said output node, a control electrode of said output transistor being responsively coupled to said input circuit   wherein said voltage-modifying circuit comprises an input node for receiving said reference voltage, first and second p-channel transistors, a first node an n-channel transistor, and an output node the n-channel transistor having its source-drain path coupled between said first node and ground;   the first p-channel transistor having its source-drain path coupled between the power supply voltage and said first node, and its gate electrode responsively coupled to said input node;   the second p-channel transistor having its source-drain path coupled between the power supply voltage and the output node, and its gate electrode coupled responsively to said first node,   the first p-channel transistor being sized relative to the n-channel transistor so that a voltage developed at said first node rises faster than it rises in the power supply voltage.   
     
     
       24. The circuit of claim 23 wherein said voltage-modifying circuit further comprises a further n-channel transistor having its source-drain path coupled between said first node and ground, and its gate electrode coupled to said input node. 
     
     
       25. A method of driving an output node in accordance with data comprising the steps of: applying the data to a first stage circuit driving its output between a derived power supply voltage and ground in accordance with the data state to provide a modified data signal;   applying the modified data signal to a control electrode of an output transistor in a subsequent stage; and   generating said derived power supply voltage by producing a voltage that is a quadratic function of a power supply voltage over a range of operating values thereof.