Structured logic design method using figures of merit and a flowchart methodology

Abstract

The present invention provides a structured integrated circuit design methodology. The methodology is based on describing a two-phase logic function using a high level behavioral description flow chart, properly sizing devices to be used in the circuit for speed and reducing trial and error in circuit layout implementation using novel chip planning techniques. The methodology begins with the definition of signal types based on the circuit function that creates a particular signal and the type of input signal that feeds the circuit function. A rigid set of rules is then established for use of the signal types. Next the technical specification of the two-phase logic function is defined and utilized to create a behavioral flow chart using defined symbols. An associated database of corresponding Boolean equations is then created that defines the parameters of the various elements of the flow chart. The Boolean equations are then converted to a logic diagram either by coded state assignment or by direct implementation. The resulting logic diagram is then analyzed for speed utilizing a Figures of Merit technique for establishing device sizes. The resulting circuit design may then be carried through to layout utilizing conventional computer aided design (CAD) tools.

We claim: 
     
       1. A computer implemented method of creating a flow chart of a two-phase logic circuit that responds to both high and low non-overlapping phases of a clock signal for data transfer by the logic circuit, wherein the computer comprises a data processing system having a memory associated therewith for storing data utilizable by the data processing system, the method comprising: defining a plurality of logic circuit functional elements, each logic circuit functional element being responsive to the high phase of the clock signal, the low phase of the clock signal, or both the high and the low phases of the clock signal for transfer of data by said logic circuit functional element; storing in the memory of the data processing system signal type data that define a plurality of signal types that categorize a signal by its timing characteristics relative to the high and low phases of the clock signal and by the logic circuit functional element that generates said signal;   storing in the memory of the data processing system utilization data that define a set of rules for utilizing the signal types in conjunction with the logic circuit functional elements such that each logic circuit functional element generates an output signal corresponding to one of the signal types in response to permissible input signal types selected from the plurality of signal types;   defining a plurality of flow chart symbols that are interconnected in accordance with the utilization data to provide a behavioral flow chart of the two-phase logic circuit, each flow chart symbol corresponding to a logic circuit functional element.   
     
     
       2. A digital computer implemented method as in claim 1 and including the further step of converting the behavioral flow chart to a corresponding set of Boolean equations. 
     
     
       3. A digital computer implemented method as in claim 2 and including the further step of converting the Boolean equations to a corresponding logic diagram. 
     
     
       4. A method of designing an integrated circuit that includes a plurality of functional elements and that implements a two-phase logic functions by responding to both high and low non-overlapping phases of a clock signal, the method comprising: defining a plurality of signal types that categorize a signal by its timing characteristics relative to the high and low phases of the clock signal and by the functional element that generates said signal;   defining a set of utilization rules for utilizing the signal types in conjunction with the functional elements such that each functional element generates an output signal corresponding to one of the signal types in response to permissible input signal types selected from the plurality of signal types;   defining a technical specification for the two-phase logic function;   defining a plurality of flow chart symbols that are interconnected in accordance with the utilization rules to provide a behavioral flow chart of the two-phase logic circuit, each flow chart symbol corresponding to a functional element of the integrated circuit;   converting the behavioral flow chart into a corresponding set of Boolean equations;   converting the set of Boolean equations into a corresponding logic diagram comprising a plurality of interconnected logic elements; and   converting the interconnected logic elements into corresponding interconnected device networks utilizing Figures of Merit such that the interconnected device networks provide a schematic circuit diagram that implements the two-phase logic function in accordance with the technical specification.   
     
     
       5. A method as in claim 4 and wherein the step of converting the logic elements into corresponding device networks includes utilization of predefined performance constants for sizing the at least one integrated circuit device to optimize the speed of the two-phase logic function.