Semiconductor integrated circuit device with power consumption reducing arrangement

Abstract

In semiconductor circuits, and particularly in memories, it is often desirable to use bipolar transistors for speed together with MOS elements. However, although the bipolar transistors are useful for speed considerations, they undesirably significantly increase the power consumption of the overall circuit. Accordingly, to reduce power consumption, a bipolar/MOSFET arrangement is provided wherein MOSFETs are used as current sources to supply operation currents to the bipolar transistors only during the periods of their operation. Thus, a semiconductor integrated circuit device is achieved featuring a high operation speed yet consuming reduced amounts of electric power. Additionally, power consumption can be further reduced by providing a time serial operation for actuation of the MOSFETs in different peripheral circuits for a memory array.

I claim: 
     
       1. A semiconductor memory device comprising: a memory array;   bipolar transistors that generate output signals during a period of their operation, wherein said bipolar transistors are coupled to said memory array;   MOSFETs coupled to said bipolar transistors and responsive to control signals for selectively providing operating current to said bipolar transistors;   an address signal detection circuit coupled to said memory array to detect addresses selected in said memory array; and   a timing generator circuit coupled to said address signal detection circuit and for forming time-serial timing signals as said control signals according to whether a writing/reading operation is to be conducted for said memory array,   wherein said MOSFETs are time-serially operated according to said time-serial timing signals.   
     
     
       2. A semiconductor memory device according to claim 1, further comprising: memory cells formed in said memory array for storing data therein, said memory cells being comprised of MOSFETs or bipolar transistors.   
     
     
       3. A semiconductor memory device according to claim 1, wherein said bipolar transistors are of an NPN type. 
     
     
       4. A semiconductor memory device according to claim 1, wherein said MOSFETs are of an N-channel type. 
     
     
       5. A semiconductor integrated circuit device comprising: a memory array including a plurality of word lines, a plurality of pairs of data lines and a plurality of memory cells coupled to said plurality of word and data lines so that each memory cell is coupled to a word line and a pair of data lines;   a read circuit, coupled to said memory array to provide output signals indicative of data stored in said memory cells, comprising: a sense amplifier including a first control MOSFET, and a pair of bipolar transistors coupled to form a differential circuit with bases thereof being coupled to a selected one of said plurality of pairs of data lines and with a common emitter thereof being coupled to said first control MOSFET to provide operating current to said differential circuit only when a first predetermined signal is received by said first control MOSFET indicating that said memory array has been selected for operation; and   a main amplifier including a pair of bipolar transistors coupled to receive collector outputs of said pair of bipolar transistors in said sense amplifier and at least one second control MOSFET coupled to provide operating current to said pair of bipolar transistors in said main amplifier when a second predetermined signal is received by said second control MOSFET indicating that said memory array has been selected,     wherein said read circuit will provide output signals indicative of data stored in said memory cells only when said first predetermined signal and said second predetermined signal indicate that said memory array has been selected for operation.   
     
     
       6. A semiconductor integrated circuit device according to claim 5, wherein said memory cells of said memory array are comprised of MOSFETs forming static memory cells. 
     
     
       7. A semiconductor integrated circuit device according to claim 5, wherein said memory cells of said memory array are comprised of bipolar transistors to form a bipolar-type RAM. 
     
     
       8. A semiconductor integrated circuit device according to claim 7, wherein said memory cell include a pair of cross-coupled bipolar transistors. 
     
     
       9. A semiconductor integrated circuit device according to claim 5, wherein said first control MOSFET is coupled to have its drain-source path coupled to said common emitter of said pair of bipolar transistors in said sense amplifier and to have its gate coupled to receive said first predetermined signal. 
     
     
       10. A semiconductor integrated circuit device according to claim 9, wherein a plurality of memory arrays are provided, each with one of said sense amplifiers coupled thereto, and further comprising a gate circuit coupled to each of said sense amplifiers to provide said first predetermined signal to said gate of said first control MOSFET of the respective sense amplifier to which said gating circuit is coupled, wherein each said gating circuit comprises means for providing said first predetermined signal to said first control MOSFET of the respective sense amplifier to which said gating circuit is coupled when the respective memory array to which said respective sense amplifier is coupled has been selected for operation. 
     
     
       11. A semiconductor integrated circuit device according to claim 5, further comprising: a writing circuit having a plurality of bipolar transistors coupled to a selected one of said plurality of pairs of data lines; and   a third control MOSFET coupled to said plurality of bipolar transistors in said writing circuit to provide an operating current to said plurality of bipolar transistors in said writing circuit when a third predetermined control signal is received by said third control MOSFET.   
     
     
       12. A semiconductor integrated circuit device according to claim 11, further comprising a data input buffer coupled between a data input terminal and said writing circuit, wherein said data input buffer includes a plurality of bipolar transistors coupled to said data input terminal and to said bipolar transistors of said writing circuit, said data input buffer further comprising a fourth control MOSFET coupled to said bipolar transistors in said data input buffer for providing an operating current to said bipolar transistors in said data input buffer when a fourth predetermined signal is received by said fourth control MOSFET. 
     
     
       13. A semiconductor integrated circuit device according to claim 12, further comprising: means for determining when an address change has been made; and   a timing generator circuit for operating said first and second or third and fourth control MOSFETs time-serially in accordance with a predetermined time series of circuit operation.   
     
     
       14. A semiconductor integrated circuit according to claim 5, wherein said pairs of bipolar transistors in said sense and main amplifiers are of an NPN type. 
     
     
       15. A semiconductor integrated circuit device according to claim 5, wherein said first and second control MOSFETs are of an N-channel type.