Address control device for effectively controlling an address storing operation even when a request is subsequently cancelled

Abstract

In an address control device operable in response to an input virtual address signal to control an access operation to a memory section, an address storing operation is started by an address conversion control section (22) when no real address part is stored in a translation lookaside buffer (21) in correspondence to the input virtual address signal. The address storing operation is continued in the address control device even when a cancellation signal is given from an execution processing unit (12) so as to cancel the access operation, without supply of a request signal to the memory section. For this purpose, an "under operation" signal is produced from an "under operation" flip-flop (46) during the address storing operation to reject reception of the cancellation signal and to hold the input virtual address in a virtual address register (20).

What is claimed is: 
     
       1. An address control system operable in response to a succession of indications, each of said indications issuing from an execution processing unit to indicate an access operation by said processing unit to access a memory section, including a main memory and a cache memory for said main memory, and each of said indications including an input virtual address, said address control system comprising: (1) high capacity address storing means, separate from said memory section, for storing a plurality of partial virtual addresses and a plurality of partial real addresses, each of said partial virtual addresses corresponding to a respective one of said partial real addresses, said address storing means, when accessed by said input virtual address indicating a required partial virtual address having a corresponding required partial real address, producing one of a presence signal and an absence signal representing, respectively, whether said required partial real address is present or absent as one of said partial real addresses in said address storing means;   (2) storing control means, responsive to said input virtual address and selectively responsive to one of said presence signal and said absence signal, for controlling said address storing means to cause said address storing means to carry out an address readout operation of said required partial real address from said address storing means in response to said presence signal or   to carry out an address accessing operation of said memory section for said required partial real address in response to said absence signal and also to carry out an address storing operation of said required partial real address from said memory section into said address storing means in response to said absence signal,   said address storing operation being executed in response to a specific one of said indications,   said specific one of said indications being followed by a subsequent one of said indications,   said subsequent one of said indications indicating cancellation of said address storing operation carried out in response to said specific one of said indications; and     (3) validity control means coupled to said storing control means and responsive to said subsequent one of said indications for causing said storing control means to validly continue to execute said address storing operation in response to said specific one of said indications even when said subsequent one of said indications indicates said cancellation of said address storing operation.   
     
     
       2. An address control system as claimed in claim 1, wherein: said address storing means comprises (a) an address storage unit for storing said plurality of partial virtual addresses and said plurality of partial real addresses,   (b) selective signal producing means responsive to said input virtual address and coupled to said storage unit for selectively producing one of said presence signal and said absence signal when said address storage unit is accessed by said input virtual address and   (c) completion signal producing means coupled to said memory section for producing a completion signal representative of completion of said address storing operation; and     said validity control means comprises (a) control signal producing means, coupled to said selective signal producing means and coupled to said completion signal producing means, for storing said absence signal until reception of said completion signal and for producing an internal control signal representing continuation of said address storing operation and   (b) rejection means, coupled to said execution processing unit and responsive to said internal control signal, for rejecting reception of said subsequent one of said indications during reception of said internal control signal for providing for said continuation of said address storing operation.     
     
     
       3. A method of controlling an access operation of an execution processing unit for accessing a memory section, including a main memory and a cache memory for said main memory, by an address control device, said address control device operating in response to a succession of indications from said execution processing unit to indicate said access operation, comprising the steps of: (1) supplying to said address control device an input virtual address included in each of said indications, said input virtual address including a required partial virtual address;   (2) storing in high capacity address storing means, separate from said memory section, located in said address control device a plurality of partial virtual addresses and a plurality of partial real addresses, each of said partial virtual addresses corresponding to a respective one of said partial real addresses;   (3) accessing said address storing means with said input virtual address to produce one of a presence signal and an absence signal, (a) said presence signal representing a presence of a required partial real address corresponding to said required partial virtual address in said address storing means and   (b) said absence signal representing an absence of said required partial real address corresponding to said required partial virtual address in said address storing means;     (4) controlling said address storing means by storing control means responsive to said input virtual address and selectively responsive to said presence signal and said absence signal to cause said address storing means to carry out one of (a) an address readout operation of said required partial real address from said address storing means in response to said presence signal; and   (b) an address storing operation of said required partial real address from said memory section into said address storing means in response to said absence signal,   said address storing operation being executed in response to a specific one of said indications,   said specific one of said indications being followed by a subsequent one of said indications indicating cancellation of said address storing operation carried out in response to said specific one of said indications; and     (5) validly continuing said address storing operation in said address control device without cancellation, even on reception of said subsequent one of said indications indicating said cancellation of said address storing operation.