Semiconductor device

Abstract

A semiconductor device including a lead frame provided with a die pad and a plurality of leads arranged around the die pad, a semiconductor element mounted on the die pad, and a molding resin for sealing the semiconductor element. A spacing defined between the die pad and the leads is sized, i.e. made very small, that a flow velocity of a first portion of the molding resin flowing in a peripheral region of the semiconductor element becomes substantially equal to a flow velocity of a second portion of the molding resin flowing on at least an upper surface of the semiconductor element. That is, the first portion of the molding resin flowing in the peripheral region of the semiconductor element receives resistance due to the very small spacing between the die pad and the leads. Accordingly, the flow of the molding resin as a whole can be made uniform to thereby reduce or eliminate the generation of voids in the molding resin. As a result, reliability and productivity of the semiconductor device can be improved.

What is claimed is: 
     
       1. In a semiconductor device including a lead frame provided with a die pad and a plurality of leads arranged around said die pad so that inner ends of said plurality of leads are adjacent to said die pad, a semiconductor element mounted on said die pad, an upper surface of said semiconductor element exhibiting a first resistance to a flow of molding resin across said upper surface thus to cause a first flow velocity of molding resin, and a molding resin for sealing said semiconductor element; the improvement wherein a space defined between said die pad and the inner ends of said leads is sized so that a flow velocity of a first portion of said molding resin flowing in a peripheral region about said semiconductor element from a source external to said lead frame becomes substantially equal to a second flow velocity of a second portion of said molding resin flowing on at least said upper surface of said semiconductor element, said peripheral region being sized so as to present a second resistance to a flow of said molding resin through said peripheral region thus to cause said first velocity. 
     
     
       2. The semiconductor device as defined in claim 1, wherein an outline of said die pad is so shaped as to correspond to a line of arrangement of said inner ends of said leads so that distances between a plurality of electrodes provided on said semiconductor element and said inner ends corresponding to said electrodes are substantially equal to one another, and a spacing between said outline of said die pad and said line of arrangement of said inner ends of said leads is uniform. 
     
     
       3. The semiconductor device as defined in claim 2, wherein said outline of said die pad is polygonal and said line of arrangement of the inner ends of said leads is congruently polygonal and uniformly spaced therefrom. 
     
     
       4. The semiconductor device as defined in claim 3 wherein said uniform spacing between the outline of said die pad and said polygonal line of arrangement of the inner ends of the inner leads is about 0.5 mm or less. 
     
     
       5. The semiconductor device as defined in claim 2 wherein said spacing between a side edge of the die pad and the line of arrangement of the inner ends of the inner leads is less than about 0.8 mm. 
     
     
       6. The semiconductor device as defined in claim 5 wherein said spacing is about 0.4 mm. 
     
     
       7. The semiconductor device as defined in claim 1, wherein a lower surface of said die pad opposite said semiconductor element exhibits a third flow resistance to said flow of said molding resin thus causing a third flow velocity of said molding resin across said lower face so that said first flow velocity of said first portion of said molding resin flowing in said peripheral region of said semiconductor element becomes substantially equal to the third flow velocity of a third portion of said molding resin flowing on a lower surface of said die pad. 
     
     
       8. The semiconductor device as defined in claim 7, wherein said first flow velocity of said first portion of said molding resin flowing in said peripheral region of said semiconductor element becomes substantially equal to said second flow velocity of said second portion of said molding resin flowing on said upper surface of said semiconductor element and said third flow velocity of said third portion of said molding resin flowing on said lower surface of said die pad. 
     
     
       9. A semiconductor device sealed with a molding resin, comprising: a lead frame;   a die pad provided on said lead frame;   a semiconductor element mounted on said die pad, an outer surface of said semiconductor element exhibiting a first flow resistance to said molding resin when molten and flowing from a location remote from said semiconductor element across said outer surface of said semiconductor element;   a plurality of inner leads arranged around said die pad adjacent said semiconductor element and having inner ends spaced therefrom at a distance sized to exhibit a second flow resistance to said molding resin when molten and flowing from said remote location through a space between said semiconductor element and said inner ends of said inner leads;   said first flow resistance and said second flow resistance to said molten molding resin causing a first flow velocity and a second flow velocity respectively, which are substantially equal, when molten resin is introduced into the semiconductor device during manufacture, whereupon voids are reduced.   
     
     
       10. The semiconductor device as defined in claim 9, wherein an outline of said die pad is so shaped as to correspond to a line of arrangement of said inner ends of said leads so that distances between a plurality of electrodes provided on said semiconductor element and said inner ends corresponding to said electrodes is substantially equal to one another, and a spacing between said outline of said die pad and said line of arrangement of said inner ends of said leads is uniform. 
     
     
       11. The semiconductor device as defined in claim 10, wherein said outline of said die pad is polygonal and said line of arrangement of the inner ends of said leads is congruently polygonal and uniformly spaced therefrom. 
     
     
       12. The semiconductor device as defined in claim 11 wherein said uniform space between the outline of said die pad and said polygonal line of arrangement of the inner ends of the inner leads is about 0.5 mm or less. 
     
     
       13. The semiconductor device as defined in claim 10 wherein said spacing between a side edge of the die pad and the line of arrangement of the inner ends of the inner leads is less than about 0.8 mm. 
     
     
       14. The semiconductor device as defined in claim 13 wherein said spacing is about 0.4 mm. 
     
     
       15. The semiconductor device as defined in claim 9, wherein a lower surface of said die pad opposite said semiconductor element exhibits a third flow resistance to said flow of said molding resin thus causing a third flow velocity of said molding resin across said lower face so that a second flow velocity of said second portion of said molding resin flowing in said peripheral region of said semiconductor element becomes substantially equal to the third flow velocity of a third portion of said molding resin flowing on a lower surface of said die pad. 
     
     
       16. The semiconductor device as defined in claim 15, wherein said first flow velocity of said first portion of said molding resin flowing in said peripheral region of said semiconductor element becomes substantially equal to said second flow velocity of said second portion of said molding resin flowing on said upper surface of said semiconductor element and said third flow velocity of said third portion of said molding resin flowing on said lower surface of said die pad. 
     
     
       17. A method of making a semiconductor device sealed with a molding resin, wherein said semiconductor device comprises a lead frame; a die pad provided on said lead frame; a semiconductor element mounted on said die pad, an outer surface of said semiconductor element exhibiting a first flow resistance to said molding resin when molten and flowing from a location remote from said semiconductor element across said outer surface of said semiconductor element; a plurality of inner leads arranged around said die pad adjacent said semiconductor element and having inner ends spaced therefrom at a distance sized to exhibit a second flow resistance to said molding resin when molten and flowing from said remote location through a space between said semiconductor element and said inner ends of said inner leads; said first flow resistance and said second flow resistance to said molten molding resin causing a first flow velocity and a second flow velocity respectively, which are substantially equal, whereupon voids are reduced, said method comprising the steps of: providing a molten resin to said location remote from said semiconductor element;   causing said molten resin to flow from said remote location to said die pad;   causing a first portion of said molten resin to flow from said die pad across said surface of said semiconductor element;   then causing a second portion of said molten resin to flow through said peripheral portion and on the inner leads;   then causing said second portion of said molten resin to flow at substantially the same velocity as said first portion when said first portion has passed over the surface of the semiconductor element.   
     
     
       18. The method as set forth in claim 17, wherein said second portion is caused to flow at a velocity just higher than that of the first portion. 
     
     
       19. The method as set forth in claim 17 further including a step of causing said molten resin to pass over a lower surface of said die pad opposite to said surface on which said semiconductor element is located, said lower surface exhibiting a third resistance to said flow, at a third flow velocity which is about the same as said first and second flow velocities. 
     
     
       20. The method as set forth in claim 17 wherein said method is carried out with epoxy resin with viscosities of 350 poise and 600 poise, wherein no voids were generated.