Address match scheme for DRAM redundancy scheme

Abstract

An address match scheme is disclosed which allows the alternate selection of fuses blown based on either logic ones or logic zeros in an address.

We claim: 
     
       1. An address match scheme for using redundant memory, comprising: a first sub-circuit including a fuse, said first sub-circuit further including a pair of cross-coupled inverters and a pair of switches, said switches being operable in connection with said fuse of said first sub-circuit to set a logic state at the input of each inverter of said cross-coupled inverters;   a first signal line coupled to said first sub-circuit;   a second signal line coupled to said first sub-circuit, operable to carry the complement of a signal on said first signal line, said signal lines being coupled to said fuse through said cross-coupled inverters;   at least one second sub-circuit coupled to said first and second signal lines, said second sub-circuit including a fuse;   said fuse of said first sub-circuit being blowable such that said fuse of said second sub-circuit can be interchanged between a scheme based on matching logic zeroes in an address and a scheme based on matching logic ones in an address.   
     
     
       2. An address match scheme for using redundant memory, comprising: a first sub-circuit including a fuse;   a first signal line coupled to said first sub-circuit;   a second signal line coupled to said first sub-circuit, operable to carry the complement of a signal on said first signal line;   at least one second sub-circuit coupled to said first and second signal lines, said second sub-circuit including a fuse, said at least one second sub-circuit further including a pair of cross-coupled inverters and a pair of switches, said switches being operable to set a logic state at the input of each inverter of said cross-coupled inverters of said at least one second sub-circuit;   said fuse of said first sub-circuit being blowable such that said fuse of said second sub-circuit can be interchanged between a scheme based on matching logic zeroes in an address and a scheme based on matching logic ones in an address.   
     
     
       3. An address match scheme as recited in claim 2 which further comprises at least one pair of switches, each switch from said at least one pair of switches being operable to transmit an address signal and the complement of said address signal to an associated transistor connected to a third signal line.