Data comparator

Abstract

According to this invention, a bit data comparing section has a plurality of groups each having a plurality of bit comparators. Each of the plurality of bit comparators compares one bit of address data input to the bit comparator with bit data stored in the bit comparator in advance and outputs a comparison result. Output data from a plurality of bit comparators belonging to one group are unified by one subsense line belonging to the group and input to a control terminal of a switching element. The switching element performs a switching operation in accordance with the input data. A main sense line is connected to the switching element, and a load circuit is connected between the main sense line and a power supply terminal.

What is claimed is: 
     
       1. A data comparator comprising: bit data comparing means having a plurality of groups, each of said groups having a plurality of bit comparators, and each of said bit comparators comprising bit data input to said each of said bit comparators with bit data stored in said each of said bit comparators in advance and outputting a comparison result;   output data coupling means having a plurality of subsense lines, each of said subsense lines arranged in a respective one of said plurality of groups, said each of said subsense lines unifying output data from bit comparators of said respective one of said groups to which said each of said subsense lines belongs;   switching means having a plurality of switching elements, each of said switching elements arranged in a respective one of said plurality of subsense lines, said each of said switching elements having a control terminal, a first terminal, and a second terminal and performing a switching operation in accordance with a potential of said respective one of said subsense lines connected to said control terminal, and said first terminal receiving a first potential, wherein each of said plurality of subsense lines is directly connected to a control terminal of one of said switching elements;   a main sense line connected to said second terminals of said plurality of switching elements; and   a load circuit having a third terminal and a fourth terminal, said third terminal being connected to said main sense line, and said fourth terminal receiving a second potential.   
     
     
       2. A comparator according to claim 1, wherein the first potential is a ground potential Vss, the second potential is a power supply potential Vcc, said load circuit is a p-channel MOSFET having a gate receiving the ground potential Vss, and each of said switching elements is an n-channel MOSFET having a gate connected to one of said subsense lines. 
     
     
       3. A comparator according to claim 1, wherein the first potential is a ground potential Vss, the second potential is a power supply potential Vcc, said load circuit is a p-channel MOSFET having a gate receiving a precharge signal, and each of said switching elements is an n-channel MOSFET having a gate connected to one of said subsense lines. 
     
     
       4. A comparator according to claim 1, wherein the first potential is a ground potential Vss, the second potential is a power supply potential Vcc, said load circuit is a pnp bipolar transistor having a base receiving the ground potential Vss, and each of said switching elements is an n-channel MOSFET having a gate connected to one of said subsense lines. 
     
     
       5. A comparator according to claim 1, wherein said first potential is a ground potential Vss, the second potential is a power supply potential Vcc, said load circuit is a pnp bipolar transistor having a base receiving a precharge signal, and each of said switching elements is an n-channel MOSFET having a gate connected to one of said subsense lines. 
     
     
       6. A comparator according to claim 1, wherein said first potential is a ground potential Vss, the second potential is a power supply potential Vcc, said load circuit is a p-channel MOSFET having a gate receiving a ground potential Vcc, and each of said switching elements is an npn bipolar transistor having a base connected to one of said subsense lines. 
     
     
       7. A comparator according to claim 1, wherein said first potential is a ground potential Vss, the second potential is a power supply potential Vcc, said load circuit is a p-channel MOSFET having a gate receiving a precharge signal, and each of said switching elements is an npn bipolar transistor having a base connected to one of said subsense lines. 
     
     
       8. A comparator according to claim 1, wherein said first potential is a ground potential Vss, the second potential is a power supply potential Vcc, said load circuit is a pnp bipolar transistor having a base receiving a ground potential Vss, and each of said switching elements is an npn bipolar transistor having a base connected to one of said subsense lines. 
     
     
       9. A comparator according to claim 1, wherein said first potential is a ground potential Vss, the second potential is a power supply potential Vcc, said load circuit is a pnp bipolar transistor having a base receiving a precharge signal, and each of said switching elements is an npn bipolar transistor having a base connected to one of said subsense lines. 
     
     
       10. A comparator according to claim 1, wherein said first potential is a power supply potential Vcc, the second potential is aground potential Vss, said load circuit is a p-channel MOSFET having a gate receiving the ground potential Vss, and each of said switching elements is an n-channel MOSFET having a gate connected to one of said subsense lines. 
     
     
       11. A comparator according to claim 1, wherein said first potential is a power supply potential Vcc, the second potential is a ground potential Vss, said load circuit is a p-channel MOSFET having a gate receiving a precharge signal, and each of said switching elements is an n-channel MOSFET having a gate connected to one of said subsense lines. 
     
     
       12. A comparator according to claim 1, wherein said first potential is a power supply potential Vcc, the second potential is a ground potential Vss, said load circuit is a pnp bipolar transistor having a base receiving the power supply potential Vss, and each of said switching elements is an n-channel MOSFET having a gate connected to one of said subsense lines. 
     
     
       13. A comparator according to claim 1, wherein said first potential is a power supply potential Vcc, the second potential is a ground potential Vss, said load circuit is a pnp bipolar transistor having a base receiving a precharge signal, and each of said switching elements is an n-channel MOSFET having a gate connected to one of said subsense lines. 
     
     
       14. A comparator according to claim 1, wherein said first potential is a power supply potential Vcc, the second potential is a ground potential Vss, said load circuit is a p-channel MOSFET having a gate receiving a ground potential Vcc, and each of said switching elements is an npn bipolar transistor having a base connected to one of said subsense lines. 
     
     
       15. A comparator according to claim 1, wherein said first potential is a power supply potential Vcc, the second potential is a ground potential Vss, said load circuit is a p-channel MOSFET having a gate receiving a precharge signal, and each of said switching elements is an npn bipolar transistor having a base connected to tone of said subsense lines. 
     
     
       16. A comparator according to claim 1, wherein said first potential is a power supply potential Vcc, the second potential is a ground potential Vss, said load circuit is a pnp bipolar transistor having a base receiving the ground potential Vss, and each of said switching elements is an npn bipolar transistor having a base connected to one of said subsense lines. 
     
     
       17. A comparator according to claim 1, wherein said first potential is a power supply potential Vcc, the second potential is a ground potential Vss, said load circuit is a pnp bipolar transistor having a base receiving a precharge signal, and each of said switching elements is an npn bipolar transistor having a base connected to one of said subsense lines. 
     
     
       18. A comparator according to claim 1, further comprising: a plurality of n-channel load MOSFETs, each of said load MOSFETS having a gate and a source, said source receiving one of said subsense lines.   
     
     
       19. A comparator according to any one of claims 3, 5, 7, 9, 11, 13, 15, and 17, further comprising: a load circuit having a plurality of n-channel MOSFETs each having a gate receiving a complementary precharge signal complementary to the precharge signal, a source receiving a power supply potential Vcc, and a drain connected to one subsense line.   
     
     
       20. A comparator according to claim 1, further comprising: a load circuit having a plurality of bipolar transistors each having a base and a collector receiving a power supply potential Vcc and an emitter connected to one subsense line.   
     
     
       21. A comparator according to any one of claims 3, 5, 7, 9, 11, 13, 15, and 17, further comprising: a load circuit having a plurality of bipolar transistors each having a base receiving a complementary precharge signal complementary to the precharge signal, a collector receiving a power supply potential Vcc, and an emitter connected to one subsense line.   
     
     
       22. A comparator according to claim 1, further comprising: a load circuit having a plurality of n-channel MOSFETs each having a gate and a source receiving a ground potential Vss and a drain connected to one subsense line.   
     
     
       23. A comparator according to any one of claims 3, 5, 7, 9, 11, 13, 15, and 17, further comprising: a plurality of n-channel load MOSFETs, each of said load MOSFETs having a gate receiving a complementary precharge signal complementary to the precharge signal, a source receiving a ground potential Vss, and a drain connected to one of said subsense lines.   
     
     
       24. A comparator according to claim 1, further comprising: a plurality of bipolar load transistors, each of said load transistors having a base and an emitter, said emitter receiving a ground potential Vss and a collector connected to one of said subsense lines.   
     
     
       25. A comparator according to any one of claims 3, 5, 7, 9, 11, 13, 15, and 17, further comprising: a plurality of bipolar load transistors, each of said load transistors having a base receiving a complementary precharge signal complementary to the precharge signal, an emitter receiving a ground potential Vss, and a collector connected to one of said subsense lines.   
     
     
       26. A comparator according to claim 1, wherein each of said bit comparators is a memory cell of a content addressable memory, and bit data input to said plurality of bit comparators are address data. 
     
     
       27. A comparator according to claim 26, wherein said content addressable memory is a tag memory section of a cache memory. 
     
     
       28. A comparator according to claim 1, wherein said main sense line and said parallel of subsense lines are arranged parallelly to each other. 
     
     
       29. A data comparator comprising: bit data comprising means having a plurality of groups, each of said groups having a plurality of bit comparators, each of said bit comparators comparing internally input bit data with prestored bit data and giving as an output a comparison result;   output data coupling means having a plurality of subsense lines, each of said subsense lines being arranged in a respective one of said groups of said bit data comparing means and unifying output data from bit comparators of said respective one of said groups to which said each of said subsense lines belongs;   switching means having a plurality of switching elements, each of said switching elements being arranged in correspondence with a respective one of said subsense lines, having a control terminal, a first terminal, and a second terminal, and performing a switching operation in accordance with a potential of said respective one of said subsense lines connected to said control terminal, and said first terminal receiving a first potential;   a main sense line connected to said second terminals of said plurality of switching elements;   a load circuit having a third terminal and a fourth terminal, said third terminal being connected to said main sense line, and said fourth terminal receiving a second potential; and   arithmetic means having a plurality of logic gate circuits, each of said logic gate circuits having a plurality of input terminals and an output terminal connected to a respective one of said subsense lines, each of said input terminals being connected to one of said plurality of bit comparators which is connected to said respective one of said subsense lines to which said output terminal is connected.   
     
     
       30. A data comparator comprising: bit data comparing means having a plurality of groups, each of said groups having a plurality of bit comparators, each of said bit comparators comparing internally input bit data with prestored bit data and giving as an output a comparison result;   output data coupling means having a plurality of subsense lines, each of said subsense lines being arranged in a respective one of said groups of said bit data comparing means and unifying output data from said bit comparators of said respective one of said groups to which said each of said subsense lines belongs;   switching means having a plurality of switching elements, each of said switching elements being arranged in correspondence with a respective one of said subsense lines, having a control terminal, a first terminal, and a second terminal, and performing a switching operation in accordance with a potential of said respective one of said subsense lines connected to said control terminal, and said first terminal receiving a first potential;   a main sense line connected to said second terminal of each of said plurality of switching elements;   a load circuit having a third terminal and a fourth terminal, said third terminal being connected to said main sense line, and said fourth terminal receiving a second potential; and   inverting means having a plurality of inverting circuits, each of said inverting circuits having an input terminal and an output terminal, said input terminal being connected to one of said subsense lines, and said output terminal being connected to a control terminal of one of said plurality of switching elements which is associated with said one of said subsense lines to which said input terminal is connected.