US5296395AExpiredUtility

Method of making a high electron mobility transistor

95
Assignee: APA OPTICS INCPriority: May 17, 1991Filed: Mar 3, 1993Granted: Mar 22, 1994
Est. expiryMay 17, 2011(expired)· nominal 20-yr term from priority
H10D 62/8503H10D 62/824H10D 30/4755Y10S977/76Y10S977/755Y10S148/072Y10S977/84Y10S148/113
95
PatentIndex Score
353
Cited by
25
References
4
Claims

Abstract

A high electron mobility transistor is disclosed, which takes advantage of the increased mobility due to a two dimensional electron gas occurring in GaN/Al x Ga 1-x N heterojunctions. These structures are deposited on basal plane sapphire using low pressure metalorganic chemical vapor deposition. The electron mobility of the heterojunction is approximately 620 cm 2 per volt second at room temperature as compared to 56 cm 2 per volt second for bulk GaN of the same thickness deposited under identical conditions. The mobility of the bulk sample peaked at 62 cm 2 per volt second at 180° K. and decreased to 19 cm 2 per volt second at 77° K. The mobility for the heterostructure, however, increased to a value of 1,600 cm 2 per volt second at 77° K. and saturated at 4° K.

Claims

exact text as granted — not AI-modified
We claim: 
     
       1. A method of making a transistor, comprising the steps of: (a) depositing a buffer layer onto a substrate;   (b) depositing a layer of gallium nitride (GaN) onto the buffer layer;   (c) depositing a layer of Al x  Ga 1-x  N on the gallium nitride layer, where x has a value of between 0 and 1;   (d) depositing a first metal layer onto the Al x  Ga 1-x  N layer, thereby defining a source connection;   (e) depositing a second metallic layer onto the Al x  Ga 1-x  N layer, thereby defining a drain region; and   (f) depositing a third metal layer, onto the Al x  Ga 1-x  N layer, the third metal layer, onto the Al x  Ga 1-x  N layer, the third metal layer residing between the source region and the drain region, thereby defining a shottky barrier.   
     
     
       2. The method of making a transistor of claim 1, further comprising the steps of: (a) connecting a first electrically conductive wire to the source region;   (b) connecting a second electrically conductive wire to the drain region; and   (c) connecting a third electrically conductive wire to the shottky barrier, thereby permitting connection of the transistor to an external circuit.   
     
     
       3. The method of making a transistor of claim 2, wherein the metal deposited to form the shottky barrier is chosen from a group including titanium, gold, aluminum, silver, chromium, tungsten, and indium. 
     
     
       4. The method of making a transistor of claim 3, wherein x is chosen to be approximately equal to 0.15.

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